pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 298

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
Access restrictions are based on the contents of the host-controlled and core-controlled access protection registers. The
access protection logic may prevent read and/or write access to addresses in the core address space. The core-controlled
register setting should always prevent host access to addresses that are not in the core domain’s base memory or expansion
memory spaces. Note that the resulting memory space is not continuous.
In DEV environment, the value of MBTA may be changed for ease of software development. The memory space between
MBTA (1 0000
The following figures illustrate the mapping function that results from the address translation function for a Shared BIOS
scheme (Figure 100) and when the flash is mapped as a non-BIOS block of memory (Figure 101).
Figure 99 illustrates the address translation scheme for shared memory transactions.
Bus
LPC
386 Mode-Compatible BIOS Range and User Defined Shared Memory Range
This address range is handled only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives);
otherwise, transactions to this zone are ignored. The address is converted to an internal address as follows:
Indirect Memory Address
This address specified in IMA3-0 is used as follows:
For allowed addresses, the SM_Host_Address is translated to a core address using the following equation
(a 21-bit address in the core address space is generated by adding the host memory address to the MBTA):
MBTA is the size of the PC87591x on-chip flash memory, as defined in the Shared Memory Main Block Top Address
register (SMCTA). This value is defined on reset to indicate the available memory size. In DEV environment, this value
may be changed to allow code development for other flash sizes.
The CR_Space_Address[21-0] is checked against the Host-Controlled Access Protection registers, the Core-Con-
trolled Override Protection registers and general address space access limitations (i.e., space not mapped to the
base memory or expansion memory).
Reset or
Core Write
SM_Host_Address[31-0] = Host_Memory_Address[31-0]
SM_Host_Address[31-0] = {IMA3[7-0], IMA2[7-0], IMA1[7-0], IMA0[7-0]}
CR_Space_Address[20-0] = (21 least significant bits)(SM_Host_Address + MBTA)
FWH ID Check
32
16
Translation
Address
in PC87591E or 2 0000
Memory R/W
Address
Figure 99. Address Translation Mechanism for 512 Kbyte On-Chip Flash
32
IMA0-3
MBTA
win_size_bits
“1”
“1”
16
17-31
in PC87591S) to F FFFF
0-(win_size_bits
0-16
Memory Address
0-31
Transaction Type &
0-31
0-31
0-31
Indirect Memory Access
386 BIOS Range
(Continued)
Decoders
Legacy & Extended
BIOS Range
31
User Def. Space
298
1)
16
is not accessible by the host.
SM_Host_Address
Host-Controlled
Protection
Registers
Access
+
0-20
Protection
Access
Logic
Core-Controlled
MBTA
Protection
Registers
Override
0-20
Core Bus
Address
Revision 1.07