pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 294

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
Host Interface PM n Control Register (HIPMnCTL)
The HIPMnCTL register controls the operation mode and configuration of the PM channel. It includes the Enhanced mode
enable bit and control bits for Enhanced mode operation. HIPMnCTL is 40
Location: Channel 1 - 00 FEB8
Type: R/W
Bit
Name
Reset
5-3
Bit
0
1
2
6
7
IBFIE (Input Buffer Full Interrupt Enabler).
0: IBF interrupt to the core is disabled
1: Enables an interrupt to the core when IBF in HIPMnST register is set
OBEIE (Output Buffer Empty Interrupt Enable).
0: OBF interrupt to the core is disabled
1: Enables an interrupt to the core when OBF in HIPMnST register is set
Reserved.
PLMS (Pulse Level Mode SCI). Sets the hardware-controlled SCI signal mode to be Level or Pulse and sets
the pulse width.
When PLMS = 000
low, and a high level is set to issue an interrupt (the respective OBF is set).
When PLMS
and it toggles high to issue an interrupt (i.e., when the respective output buffer register is written).
The pulse widths are:
Bits
5 4 3
0 0 0:
0 0 1:
0 1 0:
0 1 1:
1 0 0:
1 0 1:
Other:
SCIPOL (SCI Negative Polarity).
0: SCI output inactive value is low and its active (asserted) value is high
1: Inverted polarity is used. When SCIPOL is set, the SCI signal is the inverse of either what is stored in SCIB or
This bit affects the SCI signal polarity in both PC87570 Legacy and Enhanced modes.
EME (Enhanced Mode Enable).
0: PM channel is used in Legacy mode. HIPMnST status bits are controlled by writes to the bit value, and inter-
1: Enables enhanced control of the PM channel. The bits in HICTRL and HIIRQC registers are ignored in this case
In HIPM2CTL (i.e., for PM channel 2), EME is a read-only bit that holds the value 1. Writes to this bit are
ignored.
Channel 2 - 00 FECA
the output of the SCI pulse shaper.
rupts are controlled by HICTRL and HIIRQC register bits (default for HIPM1CTL).
(default for HIPM2CTL).
see text
EME
Pulse Width
Level interrupt
1-Cycle Pulse
2-Cycle Pulse
4-Cycle Pulse
8-Cycle Pulse
16-Cycle Pulse
Reserved
7
0, the host interrupts are in Pulse mode. In this mode, the SCI pulse shaper output value is low,
2
, the SCI signal functions in Level mode. In this mode, the SCI pulse shaper output value is
SCIPOL
16
16
6
1
5
0
(Continued)
PLMS
Description
294
4
0
16
3
0
on reset.
Reserved
2
0
OBEIE
1
0
IBFIE
Revision 1.07
0
0