pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 38

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

www.national.com
1.0 Introduction
The I/O expansion space is mapped to the address space 00 FB00
The PC87591x accesses the off-chip I/O expansion using the I/O zone of the BIU. The zone select signal (SELIO), address
lines A0-7 and the RD and WR0 signals are used to interface to the off-chip logic.
1.5.2
The host address space includes memory space and I/O space.
The I/O space used by the PC87591x is configured through the PC87591x configuration registers. The configuration register
address is defined by strap inputs (BADDR0-1) to be one of two fixed addresses or an address defined by the core using
registers in the MSWC module.
When a Shared BIOS scheme is enabled via the SHBM strap input, the PC87591x is mapped to enable the host to boot from
a shared flash device. The PC87591x supports either memory or FWH transactions for the host memory interface, with au-
tomatic selection between them (see Section 6.1.11 on page 349). Section 5.3 on page 297 discusses the mapping of mem-
ory between the host and core domains and the read and write access protection scheme from the host and core sides.
Following the boot process, the Shared Memory configuration registers (see Section 6.1.11 on page 349) enable setting
memory sharing. The configuration setting includes defining the memory protocol in use (memory or FWH) and the address
range used in the host address space. The configuration registers allow the defaults set by the SHBM strap input to be over-
ridden; this enables using the shared memory for purposes other than system BIOS (e.g., PC87591x firmware update and
secured storage of information).
1.5.3
The core may access host domain devices through the Core to Host Controlled Functions access bridge. The bridge em-
ploys an indirect mapping scheme.
There is only a single set of peripheral registers for host and core use. The bus arbitration guarantees that only one of the
two register accesses occurs at any given time, but this does not prevent problems that may be caused by conflicting write
transactions. When such a case is expected, the core lock mechanism may be used to protect access to one or more of the
devices. The lock may also be used to protect from the host from access to devices due to the security reasons.
The core accesses a register by specifying the logical device and the offset of the register within the logical device. Note that
the configuration registers’ index and data registers are also handled as a logical device. The core triggers a read by writing
1 to the read start bit and waits for the bit to clear; it can then read the data from the data register. The core triggers a write
by performing a write operation to the data register.
Section 5.4 on page 313 provides details of the bridge and its operation.
Addresses in the range 00 FB00
or in their off-chip implementation, while the chip is in DEV environment).
Address 00 FBFE
to the MCFG with the same data written to the MCFG.
Addresses in the range 00 FBC0
All other addresses may be used by the application for adding additional I/O elements.
Host Address Domain Memory Map
Core Access to Host Controlled Peripherals
16
(Continued)
is used only in DEV environment by the MCFGSH register and must be written after each write
16
16
to 00 FB22
to 00 FBFF
16
16
are used by GPIO ports PH, PI, PJ, PK, PL and PM (either on-chip
are reserved for development board use.
38
16
to 00 FBFF
16
. This space is partitioned as follows:
Revision 1.07