pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 201

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
1. Clear BER in ACBnST register and BB in ACBnCST register.
2. Wait for a time-out period to check that there is no other active master on the bus (i.e., BB in ACBnCST remains cleared).
3. Disable and then re-enable the ACB to put it in non-addressed Slave mode. (This completely resets the module.)
At this point, some of the slaves may not identify the bus error. To recover, the ACB module becomes the bus master. It
asserts a Start Condition, sends an address byte and then asserts a Stop Condition that synchronizes all the slaves.
4.13.4 Slave Mode
A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB module is enabled is not
acting as a master (i.e., MASTER in ACBnST register is cleared), it acts as a slave device.
Once a Start Condition on the bus is detected, the PC87591x checks whether the address sent by the current master match-
es any of the following possibilities:
The address match is checked even when MASTER in ACBnST register is set. If a bus conflict (on SDAn or SCLn) is de-
tected, BER is set, MASTER is cleared and the PC87591x continues to search the received message for a match.
If an address ARP or global match is detected:
1. The PC87591x asserts its SDAn pin during the acknowledge cycle.
2. MATCH in ACBnCST register, MATCHAF in ACBnST register (or GCMATCH if it is a global call address match, or ARP-
3. If INTEN in ACBnCTL1 register is set, an interrupt is generated if both INTEN and NMINTE in ACBnCTL1 register are set.
4. The software then reads XMIT in ACBnST register to identify the direction requested by the master device; it then clears
Slave Receive and Transmit
Slave Receive and Transmit are performed after a match is detected and the data transfer direction is identified. After a byte
transfer, the ACB module extends the acknowledge clock until the software reads or writes ACBnSDA register. The receive
and transmit sequences are identical to those used in the master routine.
Slave Bus Stall
When operating as a slave, the PC87591x stalls the ACCESS.bus by extending the first clock cycle of a transaction in the
following cases:
Slave Error Detection
The ACB detects illegal Start and Stop Conditions (occurring within the data transfer or the acknowledge cycle) on the AC-
CESS.bus. When an illegal Start or Stop Condition is detected, BER is set and MATCH and GMATCH are cleared, setting
the module as an unaddressed slave.
4.13.5 Power-Down
When the PC87591x is in Idle mode, the ACB module is not active but retains its status. If the ACB is enabled (ENABLE in
ACBnCTL2 register is set) on detection of a Start Condition, a wake-up signal is issued to the MIWU. This signal may be
used to switch the PC87591x to Active mode.
Following the Start Condition that woke up the PC87591x, the ACB module can not check the address byte for a match. The
ACB responds with a negative acknowledge. The device should resend both the Start Condition and the address after the
PC87591x has had time to wake up.
Before entering Idle mode, make sure that BUSY in ACBnCST register is inactive. This guarantees that the PC87591x will
not stop responding after it acknowledges an address that was sent.
4.13.6 SDA and SCL Pin Configuration
The SDAn and SCLn are open collector signals that the user can choose to enable or disable. SDAn and SCLn also have
internal pull-up resistors that the user may enable. For more information about configuring these pins, see Table 8 on
page 54 and Section 4.5.2 on page 114.
The ADDR value in ACBnADDR register, if SAEN in this register is set to 1
The ADDR value in ACBnADDR2 register, if SAEN in this register is set to 1
The global call address (00
The global ARP address (110 0001
MATCH if it is an ARP address) and NMATCH in ACBnST register are set. If XMIT in ACBnST register is set (i.e., Slave
Transmit mode), SDAST in the same register is also set to indicate that the buffer is empty.
NMATCH in the same register so that future byte transfers are identified as data bytes.
SDAST in ACBnST register is set.
NMATCH in ACBnST register and NMINTE in ACBnCTL1 register are set.
16
), if GCMEM in ACBnCTL1 register is set to 1
2
), if ARPMEN in ACBnCTL3 register is set to 1.
(Continued)
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