pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 93

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Device A Address Counter Register (ADCAn)
A double-word, read/write register. Holds the current address of either the source data item or the destination location, ac-
cording to DIR bit in DMACNTLn register. ADCAn is updated after each transfer cycle by INCAn, INCBn, ADA and ADB in
DMACNTLn register.
Location: Channel 0 - 00 FA00
Type: R/W
Device A Address Register (ADRAn)
A double-word, read/write register. Holds the starting address of either the next source data block, or the next destination data
area, according to DIR bit in DMACNTLn register.
Location: Channel 0 - 00 FA04
Type: R/W
Device B Address Counter Register (ADCBn)
A double-word, read/write register. Holds the current address of either the source data item, or the destination location, ac-
cording to DIR bit in DMACNTLn register. ADCBn is updated after each transfer cycle by INCAn, INCBn, ADA and ADB in
DMACNTLn register. In Direct (Fly-By) mode, this register is not used.
Location: Channel 0 - 00 FA08
Type: R/W
Device B Address Register (ADRBn)
A double-word, read/write register. Holds the starting address of either the next source data block or the next destination
data area, according to DIR bit in DMACNTLn register. In Direct (Fly-By) mode, this register is not used.
Location: Channel 0 - 00 FA0C
Type: R/W
Bit
Name
Bit
Name
Bit
Name
Bit
Name
Channel 1 - 00 FA20
Channel 2 - 00 FA40
Channel 3 - 00 FA60
Channel 1 - 00 FA24
Channel 2 - 00 FA44
Channel 3 - 00 FA64
Channel 1 - 00 FA28
Channel 2 - 00 FA48
Channel 3 - 00 FA68
Channel 1 - 00 FA2C
Channel 2 - 00 FA4C
Channel 3 - 00 FA6C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
(Continued)
Device A Address Counter
Device B Address Counter
Device A Address
Device B Address
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