pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 206

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
ACB Own Address Register (ACBnADDR and ACBnADDR2)
The ACBnADDR and ACBnADDR2 registers hold the module’s ACCESS.bus addresses. The reset value of these registers
are undefined.
ACBnADDR:
Location: Channel 1 - 00 FF68
ACBnADDR2:
Location: Channel 1- 00 FE6C
Type: R/W
ACB Control Register 2 (ACBnCTL2)
The ACBnCTL2 register enables/disables the module and determines the ACB clock rate. On reset and while the module is
disabled (ENABLE in ACBnCTL2 register is set to 0), ACBnCTL2 is cleared (00
Location: Channel 1 - 00 FF6A
Type: R/W
Bit
Name
Bit
Name
Reset
6-0
7-1
Bit
Bit
7
0
ADDR (Address). Holds the 7-bit ACCESS.bus address of the PC87591x. When in Slave mode, the first seven
bits received after a Start Condition are compared to this field (the first bit received is compared to bit 6, the next
bit to bit 5 and so on until the last bit, which is compared to bit 0). If the address field matches the received data
and SAEN in ACBnADDR register is set to 1, a match is declared.
SAEN (Slave Address Enable). When set (1), indicates that the ADDR field holds a valid address and enables
the match of ADDR to an incoming address byte. When cleared, the ACB does not check for an address match.
ENABLE. When set, the ACB module is enabled. When the Enable bit is cleared, the ACB module is disabled,
ACBnCTL1, ACBnST and ACBnCST are cleared and the clocks are halted.
SCLFRQ6-0 (SCL Frequency bits 6 through 0). This field, together with SCLFRQ8-7 in ACBCTL3 register,
defines the SCL’s period (low time and high time) when the PC87591x serves as a bus master. The clock low
time and high time are defined as follows:
where t
SCLFRQ may be programed to values in the range of 00 0001000
outside this range gives unpredictable results.
Channel 2 - 00 FFE8
Channel 2- 00 FFEC
Channel 2 - 00 FFEA
t
t
SCL
SCLl
CLK
SAEN
=4*SCLFRQ*t
= t
7
7
0
is the PC87591x clock cycle when in Active mode (see Section 7.6.3 on page 385).
SCLh
16
16
16
16
16
16
CLK
6
6
0
(Continued)
5
5
0
SCLFRQ6-0
Description
Description
206
4
4
0
ADDR
3
3
0
2
(8
16
10
).
) through 11 1111111
2
2
0
1
1
0
2
(511
10
ENABLE
). Values
Revision 1.07
0
0
0