pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 82

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pc87591l

Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet

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4.0 Embedded Controller Modules
Core Bus Monitoring
The core bus monitoring cycle is a non-data transfer bus cycle. It takes a single clock cycle - T1. On this cycle:
The core bus monitoring cycle, as shown in Figure 26, is generated only when bit 1 (OBR) in BCFG register is 1.
The address pins display the address of the internal device accessed on the core bus.
CBRD indicates the direction of the access (read or write).
BE0-1 indicate which data bus bytes are accessed (lower or upper).
BST0-2 display the core bus status.
Bus State
Figure 26. Core Bus Monitoring Bus Cycle
CLK
A0-12,
A16-19
SEL0-1
SELIO
BE0-1
WR0-1
D0-15
CBRD
RD
BST0-2
(Continued)
T1
82
Revision 1.07

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