pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 74

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
4.1.5
If EWR in BCFG register is 0, the BIU uses the late write bus cycle. The basic late write bus cycle takes two clock cycles.
This write bus cycle requires the RD signal in the memory device interface.
A write bus cycle starts at T1. When the data bus is in TRI-STATE, the address is placed on the address bus and SELn (or
SELIO) is activated. Next, WR0-1 are activated. RD is inactive to indicate this is a write transaction.
Late Write Bus Cycle
Bus State
Bus State
CLK
A0-19
SELx
SELy
D0-15
RD
WR0-1
BST0-2
CLK
A0-19
SELn
D0-15
RD
WR0-1
BST0-2
(x
(y
Figure 13. Early Write Following Normal Read with 0 Wait
Figure 14. Early Write Bus Cycle with 1 Internal Wait and 1 Hold
y)
x)
T1
Normal Read
T1
(Continued)
T2
TIW
In
74
T1
T2
Out
Early Write
T2
T3
Out
T
T3
Hold
All Other Zones
T1
Read,
(Note)
T2
In
Revision 1.07