pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 290

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

5.0 Host Controller Interface Modules
(Continued)
Host Data Write to Host PM Channel
The data buffer has two latches: one serves as an input buffer and the other serves as an output buffer. When writing to the
Command (legacy address 66
) or Data (legacy address 62
) registers, the following sequence occurs: data is written to
16
16
the Data In latch (DBBIN), IBF bit in the Status register is set and bit 3 (A2) in the Status register indicates to the core which
of the two addresses was written to. When writing to the data register address, A2 bit of the Status register is cleared (0).
When writing to the Command register address, A2 bit in the Status register is set (1).
The core identifies that data is present in the input buffer by either polling IBF bit in the Status register or acknowledging an
interrupt when the input buffer interrupt is enabled (IBFCIE bit in HICTRL register is set to 1).
When the input buffer is full, the Status register should be read to identify which addresses were written to by checking A2
bit in HIPMnST register. The core can then read the data from the input buffer (HIPMnDI or HIPMnDIC registers). The IBF
status bit is cleared when the data input buffer is read by the core.
Host Data Read from Host Interface Power Management Channel
The core writes to the Output Data latch (DBBOUT) when it needs to send data to the host. The OBF flag in the Status reg-
ister (HIPMnST) is set to indicate that data is available in DBBOUT. DBBOUT should be written to only when OBF in
HIPMnST register is cleared.
The PC87591x supports polling and interrupt communication schemes with the host. IRQ, SMI or SCI interrupts may be
used. The core firmware writes data addressed to the PM drivers to the HIPMnDO register. When working in Enhanced PM
mode, writes to HIPMnDOC and HIPMnDOM may be used to automatically generate SCI and SMI, respectively. Refer to
“Host Interrupt Generation Modes” on page 287 for details of the interrupt generation scheme.
The host processor identifies the presence of data in the output buffer by either polling the Status register or by responding
to IRQ, SMI or SCI events. When such data is available, the host can read it using a read operation from the address of the
data register (legacy 62
for channel 1). Reading from the data register clears the OBF flag (HIPMnST). In addition, when
16
the host interrupt is in level mode (IRQM in HIIRQC register is set to 000
) and the hardware interrupt is enabled, the IRQ
2
signal is de-asserted (low).
The core can read OBF in HIPMnST register to identify when the output buffer is empty and ready for a new data transfer.
When the output buffer empty interrupt to the core is enabled (PMOCIE bit in HICTRL register is 1 when EME bit in HIP-
MnCTL register is 0), the interrupt signal to the ICU is set high if the output buffer is empty (OBF is set to 0).
5.2.3
Core PM Registers
For a summary of the abbreviations used for Register Type, see Section 2 on page 34.
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