pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 220

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Access Paths
The flash memory can be read, written and erased through several access paths with different levels of protection for the
flash contents. Each of these paths can be operational in only some of the environments (i.e., IRE, OBD, DEV or PROG).
The flash access paths are:
The host and core use core bus read write transactions to access the flash. The JTAG and Parallel Interfaces have dedicated
access paths. An arbitration scheme selects the active interface that accesses the flash at any given time. The host and core
accesses may interleave. JTAG flash access is enabled in OBD and ENV environments when the appropriate enable bits
are set (see “Flash Interface Functional Description” on page 251 for the access enabling scheme). The Parallel interface
is enabled in PROG environment only.
Table 30 summarizes the flash information accessibility, the restrictions that apply in the various environments and the pro-
tection bit settings for each of the memory areas. Details of read, write and erase access are provided in Section 4.16.4 on
page 224. The following notation is used:
Host interface
CR16B core
JTAG flash access
Parallel interface
NA
RO
RW
RWE - Read, Write and Erase
RWe - Read, Write and a limited Erase (i.e., entire flash erase only).
Core Bus
Parallel I/Fs
JTAG I/F
- Not accessible
- Read only
- Read, Write
Core
Figure 76. On-Chip Flash Block Diagram
(Continued)
Main Block
Arbitration
Access
Control
Shared BIOS
Security
and
220
Information Block
Protection
Timing
To Host
Revision 1.07