pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 369

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host-Controlled Modules and Host Interface
RTC Control Register C (CRC)
Location: Index 0C
Type: RO
Bit
Name
Reset
3-0
Bit
Bit
3
4
5
6
7
4
5
6
7
Reserved. This bit is defined as “Square Wave Enable” by MC146818 and is not supported by the RTC. It is
always read as 0.
Update Ended Interrupt Enable. This interrupt is generated when an update occurs. It is cleared to 0 on RTC
reset (i.e., host domain reset) or when the RTC is disabled.
0: Disabled
1: Enabled
Alarm Interrupt Enable. This interrupt is generated immediately after a time update in which the seconds,
minutes, hours, date and month time equal their respective alarm counterparts. It is cleared to 0 as long as bit
7 of CRD register is 0.
0: Disabled
1: Enabled
Periodic Interrupt Enable. Bits 3-0 of CRA register determine the rate at which this interrupt is generated. It is
cleared to 0 on RTC reset (i.e., host domain reset) or when RTC is disabled.
0: Disabled
1: Enabled
Set Mode. This bit is reset at V
0: Timing updates occur normally
1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs
Reserved.
Update Ended Interrupt Flag. This RO bit is cleared to 0 on RTC reset (i.e., host domain reset) or when the
RTC is disabled. In addition, this bit is cleared to 0 when this register is read.
0: No update occurred since the last read
1: Time registers update
Alarm Interrupt Flag. This RO bit is cleared to 0 as long as bit 7 of CRD register is 0. In addition, this bit is
cleared to 0 when this register is read.
0: No alarm detected since the last read
1: Alarm condition detected
Periodic Interrupt Flag. This RO bit is cleared to 0 on RTC reset (i.e., host domain reset) or when the RTC is
disabled. In addition, this bit is cleared to 0 when this register is read.
0: No transition occurred on the selected tap since the last read
1: Transition occurred on the selected tap of the divider chain
IRQF (IRQ Flag). This RO bit mirrors the value of the interrupt output signal. When interrupt is active, IRQF is
1. To clear this bit (and deactivate the interrupt), read CRC register; this clears flags UF, AF and PF, which
results in IRQF being cleared, as well.
0: IRQ inactive
1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF))
IRQF
16
7
0
Interrupt
Periodic
Flag
6
0
PP
Interrupt
Power-Up reset only.
Alarm
Flag
5
0
Interrupt
Update
Ended
Flag
Description
Description
369
4
0
(Continued)
3
0
2
0
Reserved
1
0
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