pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 303

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
5.3.6
The PC87591S includes a Random Number Generator unit. Once enabled, this unit can provide up to 800 random bits per
second. The random bits may be read one byte at a time from RNGD register when DVALID bit in RNGCS register is set.
Note that a double buffer scheme is used to improve the performance of bit gathering. The randomization of the data is ver-
ified by compliance with FIPS140-1 specifications.
5.3.7
For memory update operations, the host may need to exchange signals (indicating the state) with the core. The Signaling
interface supports this scheme. The scheme is designed mainly for polling-based operations, but it allows the host to inter-
rupt the core.
The signaling hardware includes an 8-bit register that may be read by both host and core. The host may modify bits 0 through
3 of this register; the core may modify bits 4 through 7. A host write to the register sets the Host Semaphore Write (HSEMW)
bit in the Shared Memory Core Control and Status register (SMCCST); if the interrupt enable bit (HSEMIE in SMCCST reg-
ister) is set, the shared memory interrupt to the core is set.
5.3.8
The following set of registers is accessible only by the host. The registers are maintained by V
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
Shared Memory Host Register Map
Random Number Generator (PC87591S)
Signaling Interface
Shared Memory Host Registers
Offset
0C
00
01
02
03
04
05
06
07
08
16
16
16
16
16
16
16
16
16
16
SMIMA0
SMIMA1
SMIMA2
SMIMA3
SMIMD
SMHC
SMHST
SMHAP1
SMHAP2
SMHSEM
Mnemonic
CSEM(3-0)
Shared Memory Host Semaphore
Shared Memory Indirect Memory Address 0
Shared Memory Indirect Memory Address 1
Shared Memory Indirect Memory Address 2
Shared Memory Indirect Memory Address 3
Shared Memory Indirect Memory Data
Shared Memory Host Control
Shared Memory Host Status
Shared Memory Host Access Protect 1
Shared Memory Host Access Protect 2
Figure 103. Signaling Interface
Host Side
Core Side
(Continued)
HSEM(3-0)
Register Name
303
HSEMW
Writes
DD
Varies per bit
Varies per bit
Varies per bit
Varies per bit
.
Type
R/W
R/W
R/W
R/W
R/W
R/W
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