pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 131

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
PS/2 Output Signal Register (PSOSIG)
The PSOSIG register is a byte-wide, read/write register. It allows setting the value of the PS/2 port signals. When the shift
mechanism is enabled, the clock control bits in this register define the active channel(s). On reset, this register is set to 47
Location: 00 FE86
Type: R/W
Bit
Name
Reset
6-4
Bit
Bit
7
0
1
2
IDB (Input Debounce). Defines the number of PC87591x clock cycles during which the clock input is expected
to be stable before the shift mechanism identifies its new value. This protects the shift mechanism from false
edge detections. The number of PC87591x clock cycles for which the input should be stable before an edge is
detected is as follows:
Bits
6 5 4
0 0 0:
0 0 1:
0 1 0:
0 1 1:
1 0 0:
1 0 1:
WPUEN (Weak Pull-Up Enable).
0: The pull-up is disabled. In this state, the system must ensure that PS/2 interface signals are not floating, to en-
1: Enables the internal pull-up of the output buffer. The pull-up remains active as long as the buffer does not drive
WDAT1 (Write Data Signal Channel 1). Controls the data output to channel 1 data signal (PSDAT1). Use of
this bit depends on whether or not the shift mechanism is enabled.
Note: WDAT1 is set by the hardware after the PC87591x detected a start bit (i.e., on entering Transmit Active
WDAT2 (Write Data Signal Channel 2). Controls the data output to channel 2 data signal (PSDAT2). For more
information, see the description of bit 1 (above).
WDAT3 (Write Data Signal Channel 3). Controls the data output to channel 3 data signal (PSDAT3). For more
information, see the description of bit 1 (above).
able proper PS/2 operation.
the signal to low level.
When the shift mechanism is disabled (EN bit in PSCON register is set to 0), the data in WDAT1 is output to
PSDAT1 signal.
When the shift mechanism is enabled (EN=1), WDAT1 should be set to 1, except when the shift mechanism is
in Transmit mode. In this case, when in transmit-inactive and it is intended to transmit data to channel 1, the
firmware should clear WDAT1 bit to force the transmit signaling (low) to the PS/2 device.
If WDAT1 is cleared (0), the output buffer data is 0 (i.e., PSDAT1 is forced low).
If WDAT1 is set (1), the output buffer data is 1 (i.e., PSDAT1 is pulled high by the internal pull-up and may
be pulled low by an external device).
state). If a transmission is aborted before Transmit Active state, WDAT1 should be set (1) prior to disabling
the channel.
CLK4
16
Description
One cycle
Two cycles
Four cycles
Eight cycles
16 cycles
32 cycles
7
0
WDAT4
6
1
(Continued)
CLK3
5
0
CLK2
Description
Description
131
4
0
CLK1
3
0
WDAT3
2
1
WDAT2
1
1
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WDAT1
0
1
16
.