pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 330

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
MSWC Control Status Register 2 (MSWCTL2)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. Bits in this register
are cleared by V
Location: 00 FCC2
Type: Varies per bit
MSWC Control Status Register 3 (MSWCTL3)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of
this register is preserved by V
Location: 00 FCC4
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
5-1 R/W1C ACPIS1-5 (ACPI request for S1 through S5). These bits may be used by ACPI software to directly
Bit
0
6
7
R/W1C ACPIS0 (ACPI request for S0). This bit may be used by ACPI software to directly request a change of
Type
RO
RO
CFGPSO
power state. This bit is set when the host software writes a value of 0 to bits S1 through S5 in
WK_STATE register. This bit is cleared by writing 1 to it. A write of 0 is ignored.
0: No pending request for S0 change (default)
1: A request for S0 change was detected
request a change of power state. These bits are set by a host software write of 1 to the respective bit in
WK_STATE register. The bit is cleared by writing 1 to it. A write of 0 is ignored.
When any ACPIS0 through ACPIS5 bit is set, an APC interrupt to the core, using a MIWU input, is
asserted.
CFGPBM (SuperI/O Configuration Register D Power Button Mode). This bit reflects the current status
of the Power Button Mode bit in SIOCFD register. This bit may be used by the host software to specify
to the core he method used for power off signaling. See “SuperI/O Configuration D Register (SIOCFD)”
on page 347
A write of 1 clears the interrupt signal caused by a change in this bit value. A write of 0 to this bit is
ignored.
CFGPSO (SuperI/O Configuration Register D Power Supply Off). This bit is set whenever a 1 is
written to the Power Supply Off bit in SIOCFD register. This bit may be used by the host software to
specify to the core that the power supply should be turned off, in a non-ACPI system. See “SuperI/O
Configuration D Register (SIOCFD)” on page 347.
A write of 1 clears this bit and the interrupt signal caused by a change in this bit value. A write of 0 to
this bit is ignored.
CC
16
16
Power-Up and RESET1 resets.
7
0
7
0
CFGPBM
PP
and it is reset only on V
6
0
6
0
Reserved
ACPIS5
5
0
5
0
(Continued)
PP
ACPIS4
Power-Up reset.
330
4
0
4
0
Description
ACPIS3
3
0
3
0
ACPIS2
RTCAL
2
0
2
0
ACPIS1
LPFTO
1
0
1
0
ACPIS0
HRAPU
Revision 1.07
0
0
0
1