pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 113

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
4.5
The PC87591x includes four types of General-Purpose I/O (GPIO) ports: Px, Py, Pz and Pw.
The GPIO signals are organized in ports. Each port is either 8-bits or 16-bits wide. In ports where not all eight bits are used,
some of the register’s bits are reserved. Some GPIO signals share their pins with one or more alternate functions. A config-
uration bit selects which function is active (see Section 2.4 on page 54).
Note: Some GPIO signals are only available in a 176-pin package.
GPIO Port Functionality
The PC87591x provides 117 GPIO pins in the 176-pin package and 84 GPIO pins in the 128-pin package. They are subdi-
vided into the following groups:
Px signals: Each signal is bidirectional and can be configured as input or output. An internal weak pull-up is provided
to hold the pin high when used as an input or in an open-drain scheme.
Py signals: Each signal is input only. An internal weak pull-up is provided to hold the pin high.
Pz signals: Each signal is output only. It may be configured to work as totem-pole or in an open-drain scheme.
Pw signals: Each signal is bidirectional and can be configured for input or output. The Pw pins may be shared with
development system functions. These ports can be implemented off-chip in DEV environment using external logic.
Ports IOPA(7-0), IOPB(7-0), IOPC(7-0), IOPD(7-0) and IOPF(7-0)
These ports are on-chip, General-Purpose Input/Output (GPIO) ports (type Px).
IOPC0 is reserved for power supply control use. Bit 0 of PCALT, PCDIR, PCWPU and PCDOUT are reset on V
Up reset and WATCHDOG reset only.
PB5 and PB6 have an option for automatic TRI-STATE based on LPCPD. See “MSWC Control Status Register 3
(MSWCTL3)” on page 330 for the enable function.
PB6 is selected to its alternate function, by default (i.e., bit 6 is set to 1).
Ports IOPA4-0, IOPB2-0, IOPC0 and IOPD3 have the option to echo the value of the associated input. For the exact
echo matrix specifications, see Section 2.4.3 on page 59.
Bit 5 of PBALT register, bit 0 of PCALT register and bits 4-7 of PDALT register are read only (RO) and return a value of
zero.
IOPE(7-0) and KBSIN(7-0)
These are General-Purpose Input (GPI) ports (type Py). IOPE(3-0) and IOPE5 do not implement the pull-up function,
and the respective bits in PEWPU are reserved. KBSIN has no alternate function; thus it has no PyALT register.
KBSOUT(15-0)
This is a 16-bit General-Purpose Output (GPO) port (type Pz). Since KBSOUT has no alternate functions, its alter-
nate function register is not implemented. The reset value of KBSOUT register is FFFF
output drivers.
Ports IOPH(7-0), IOPI(7-0), IOPJ(7-0), IOPK(7-0),IOPL(4-0) and IOPM(7-0)
These ports are on-chip, General-Purpose Input/Output (GPIO) ports (type Pw).
When the analog function is enable, the Read function, for GPIO signals that are multiplexed with analog functions,
is disabled; this affects signals KBSIN(7-0) and IOPE(3-0).
When the BIU function is enabled, the Read function, for GPIO signals that are multiplexed with BIU signals, is dis-
abled; this affects signals PH(7-0), PI(7-0), PJ(1-0), PK(7-0), PL(7-0) and PM(7-0).
GENERAL-PURPOSE I/O (GPIO) PORTS
(Continued)
113
16
. KBSOUT has open-drain
www.national.com
CC
Power-