pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 16

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Table of Contents
5.0 Host Controller Interface Modules
5.1
5.2
5.3
4.20.8
KEYBOARD AND MOUSE CONTROLLER INTERFACE ....................................................... 277
5.1.1
5.1.2
5.1.3
5.1.4
POWER MANAGEMENT (PM) CHANNELS ........................................................................... 285
5.2.1
5.2.2
5.2.3
SHARED MEMORY AND SECURITY ..................................................................................... 297
5.3.1
5.3.2
5.3.3
CR16B Development Support Registers ................................................................... 275
Features .................................................................................................................... 277
General Description ................................................................................................... 277
Host Interface Registers ............................................................................................ 280
Core Interface Registers ............................................................................................ 282
Features .................................................................................................................... 285
General Description ................................................................................................... 286
Core PM Registers .................................................................................................... 290
Host Bus to Core Bus Access Translation ................................................................. 297
Memory Mapping and Host Address Translation ...................................................... 297
Indirect Memory Read and Write Transaction ........................................................... 300
(Continued)
Debug Configuration Register (DBGCFG) ......................................................... 275
Debug Freeze Enable Register (DBGFRZEN) .................................................. 276
Host Addresses ................................................................................................. 277
Core Interrupts ................................................................................................... 277
Host Interrupts ................................................................................................... 277
Keyboard/Mouse Channel (6016, 6416) ............................................................ 278
Status Read ....................................................................................................... 279
Host Interface Register Map ............................................................................. 280
Data Out Buffer Register (DBBOUT, Legacy 6016) .......................................... 280
Status Register (STATUS, Legacy 6416) .......................................................... 281
Data In Buffer Register (DBBIN, Legacy 6016) ................................................. 281
Command In Buffer Register (COMAND, Legacy 6416) ................................... 281
Core Interface Register Map .............................................................................. 282
Host Interface Control Register (HICTRL) ......................................................... 282
Host Interface IRQ Control Register (HIIRQC) .................................................. 283
Host Interface Keyboard/Mouse Status Register (HIKMST) .............................. 284
Host Interface Keyboard Data Out Buffer Register (HIKDO) ............................. 284
Host Interface Mouse Data Out Buffer Register (HIMDO) ................................. 285
Host Interface Keyboard/Mouse Data In Buffer Register (HIKMDI) ................... 285
Host Addresses ................................................................................................. 286
Core Interrupts ................................................................................................... 287
Host Interrupt Generation Modes ...................................................................... 287
Status Read ....................................................................................................... 289
Host Data Read from Host Interface Power Management Channel .................. 290
Core PM Register Map ...................................................................................... 291
Host Interface PM n Status Register (HIPMnST) .............................................. 291
Host Interface PM n Data Out Buffer (HIPMnDO) ............................................. 292
Host Interface PM n Data Out Buffer with SCI (HIPMnDOC) ............................ 292
Host Interface PM n Data Out Buffer with SMI (HIPMnDOM) ........................... 292
Host Interface PM n Data In Buffer (HIPMnDI) .................................................. 293
Host Interface PM n Data In Buffer with SCI (HIPMnDIC) ................................. 293
Host Interface PM n Control Register (HIPMnCTL) ........................................... 294
Host Interface PM n Interrupt Control Register (HIPMnIC) ................................ 295
Host Interface PM n Interrupt Enable Register (HIPMnIE) ................................ 296
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Revision 1.07