pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 302

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

www.national.com
Host Controller Interface Modules
The block number may be calculated using the following equation:
The Shared Memory Core Override Read Protect 0-2 registers and Shared Memory Core Override Write Protect 0-2 regis-
ters provide core access to the read and write protect bits, respectively. Bits in these registers may be set and cleared by
writing to the registers.
Response to a Restricted Access
A restricted access is an access that complies with at least one of the following conditions:
The PC87591x responds to a restricted access by generating an interrupt (if enabled by HERRIEN bit in SMCCST register)
to the core. Two status bits (HWERR and HRERR) indicate whether the restricted access is a read or write access. The
response on the host bus is according to the HERES field.
For restricted write accesses: Data written is ignored; when the HERES field is 10
with an error SYNC; otherwise, it is completed with a ready SYNC.
For restricted read accesses: When the HERES field is 00
access becomes unrestricted or the HERES field is changed). When the field is 01
with a ready SYNC and data of 00
The access type (i.e., Read or Write) of the translated host address (i.e., core address) is protected.
A reset to the core domain due to a Warm reset event or a flash empty indication is set (Core Boot Block field of the
protection word is 1111
Core_Block_Number = (CR_Space_Address < 128K) ?
Host Block
Figure 102. Protection Blocks for Protection Bits and Override Protection Bits
Index
31
17
16
15
3
2
1
0
2
).
Core Address
16
Address in
1F FFFF
1F 0000
0F 0000
00 E000
12 0000
11 0000
10 0000
04 0000
03 0000
02 0000
01 0000
00 0000
; when the field is 10
CR_Space_Address[20-0] / 64K : CR_Space_Address[20-0] / 8K
Space
~ ~
64K
64K
(Continued)
2
2
, the read or write transaction drives Long Wait (endlessly, unless the
, it completes the transaction with an error SYNC and data of 00
64K
64K
64K
64K
64K
64K
302
8K
8K
8K
8K
8K
8K
8K
~ ~
~ ~
Core Override
Block Number
~ ~
LA 15
LA 8
LA 6
LA 2
LA 1
LA 0
31
17
16
15
3
2
2
2
, the read or write transaction is completed
, the PC87591x completes the transaction
MBTA
Area Not Accessible
to Host
Revision 1.07
16
.