pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 320

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz
cycle). A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot
in which no RING falling edge is detected. This detection method guarantees the detection of a RING pulse train with fre-
quencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz and may detect pulses between 10 Hz
and 16 Hz.
ACPI State Change and Legacy Off Events
The host may operate in either Legacy or ACPI mode. The operation mode is specified by the Power Button Mode bit in
SuperI/O Configuration D register (SIOCFD). When EICFGPBM bit in MSIEN2 register is set, a change to the Power Button
Mode bit generates an interrupt to the core. The core may read the value of the Power Button Mode bit, using CFGPBM bit
in MSWCTL2 register, to determine how to interpret the other power state request bits.
The Power Supply Off bit in SIOCFD register may be used in Legacy mode to indicate a request to turn power off. A write
of 1 to this bit sets CFGPSO bit in MSWCTL2 register; then, if EICFGPSO bit in MSIEN2 register is set, an interrupt to the
core is generated, indicating the event.
A set of System State Change Request bits (S1-S5) are provided in WK_STATE register. The host uses these bits for ACPI-
compliant state change requests. A write of 1 to any of these bits indicates a state change request to the core through the
respective bit in MSWCTL2 register. When all bits in WK_STATE are written with 0, a request of S0 is indicated, and ACPIS0
bit in MSWCTL2 register is set. When any S0-S5 bit in MSWCTL2 is set and the respective mask bit in MSIEN2 register is
set, an interrupt to the core is generated whenever a change to any of the state bits is detected.
All interrupt requests may be cleared by writing 1 to the corresponding status bit or by masking the event (by clearing the
corresponding Interrupt Enable bit).
RTC Alarm
The RTC module may generate an ALARM signal (see Section 6.2.8 on page 359). The RTC alarm can serve as a wake-
up request to wake up the system; the request is routed to the core, which then wakes up the system. To enable an alarm
wake-up, the following settings should be made:
After an ALARM event is detected in the RTC, the RTC ALARM status bit is set (bit 5 in CRC register, page 369); in re-
sponse, RTCAL bit in MSWCTL3 register is set.
When handling an ALARM event, make sure that no events are lost by clearing RTCAL bit before clearing the ALARM status
in the RTC.
5.5.3
The MSWC generates four types of output events:
Figure 105 illustrates the enabling mechanism and the event generation scheme for the various output events. Output
events to the host are generated for input events that have their status bit set (WK_STSn.i is 1). Output events to the core,
through the MIWU, are generated for input events that have their core status bit set (MSHESn.ii is 1).
Each of the three Host Wake-Up Event Routing Control registers (WK_ENn, WK_SMIENn and WK_IRQENn) holds a Rout-
ing Enable bit for each event; this allows selective routing of these events to PWUREQ, SMI and/or the assigned MSWC
interrupt request (IRQ) channel, respectively.
After an output event is asserted, it is active until all set status bits are cleared or masked. The current status of the event
may be read at the ACPI status registers in the chipset’s ACPI controller or by reading “Wake-Up Event Status Register 0
(WK_STS0)” on page 323 and “Wake-Up Signals Value Register (WK_SIGV)” on page 325.
As shown in Figure 106, for SMI output events, the MSWC combines the event request coming from the Host Interface’s
Power Management channels 1 and 2 with MSWC internal SMI events; for PWUREQ output events, the MSWC combines
the PWUREQ events generated in the MSWC module with wake-up requests associated with the IRQ configuration regis-
ters.
Set the Alarm conditions in the RTC module. By masking the various interrupts, software may select a wake-up either
to the host directly, using the RTC’s IRQ, or to the core through the Alarm signal.
Enable the Wake-Up on Alarm status interrupt masking (optional, for Interrupt Enabled mode) by setting EIRTCAL bit
in MSIEN2 register.
Verify that the RTCAL bit in MSWCTL3 bit is cleared (no pending Alarm request).
Enable the Wake-Up on MSWC event in the MIWU and ICU modules.
Verify that the ALARM bit in the RTC is cleared.
IRQ - an interrupt routed as configured in the MSWC PnP configuration registers.
PWUREQ - an event that is typically routed to an input in the chipset that triggers an SCI event.
SMI - an event typically connected to an input in the chipset that triggers an SMI event.
MSWCI - an interrupt to the MIWU module in the core domain. This enables the core firmware to handle the wake-
up events.
Wake-Up Output Events
(Continued)
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