pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 48

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
2.2.7
Host Interface
CLKRUN
GA20
KBRST
LAD0-3
LCLK
ECSCI
LDRQ
LFRAME
LPCPD
RESET1
RESET2
PWUREQ
SERIRQ
SMI
Signal
128-Pin
21
5
6
10-13
16
25
8
9
20
17
24/123 30/165
19
7
18
LQFP
25
5
6
10
18
8
9
7
22
176-Pin
15-13,
31
24
19
23
LQFP
I/O
I/O IN
I/O IN
I/O IN
I/O IN
O
O
O
O
O
I
I
I
I
I
Buffer
PCI
PCI
TS
PCI
IN
O
IN
IN
IN
Type
O
IN
O
O
O
2/12
/OD
PCI
1/2
1/2
PCI
PCI
PCI
PCI
1/2
/O
CS
/O
/OD
PCI
PCI
12
6
Power
Well
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
CC
CC
DD
DD
CC
DD
DD
CC
CC
DD
CC
DD
CC
48
Clock Run. Same as PCI CLKRUN. When
high, indicates that the LPC clock will be slowed
down or stopped. In this case, the PC87591x
may pull it down to request full speed of the
clock.
Gate A20. Implemented using IOPB5 port
output. See Section 5.5.4 on page 322 for
signal operation and behavior when V
down.
Keyboard Reset Output. See Section 5.5.4
on page 322 for signal operation and behavior
when V
LPC Address-Data. Multiplexed command,
address bidirectional data and cycle status.
LPC Clock. Practically the PCI clock (up to 33
MHz).
EC SCI. Generates an Embedded Controller
SCI interrupt to the chipset. This signal is
typically connected to one of the chipset GPI
inputs.
LPC DMA Request. Encoded Bus Master
request for LPC I/F.
LPC Frame. Low pulse indicates the beginning
of a new LPC cycle or the termination of a
broken cycle.
Power Down. Indicates that power will be shut
off on the LPC interface.
Reset 1. A falling edge on this signal starts a
reset sequence of the PC87591x. For details,
see details in Section 3.2 on page 65.
Reset 2. A level low reset to the LPC interface
and Host Controlled Functions configuration
registers and Shared Memory host registers.
For details, see Section 3.2 on page 65.
RESET2 is either assigned to one of two
optional pins or it is disabled, as defined in the
protection words stored in the flash memory.
See Section 2.4.1 on page 54 and
Section 4.16.6 on page 226 for the
configuration of this signal.
Power-Up Request.
Serial IRQ. The interrupt requests are
serialized over a single pin, where each IRQ
level is delivered during a designated time slot.
System Management Interrupt.
(Continued)
DD
is down.
Description
DD
is
Revision 1.07