TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 95

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

HDMAMn
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
(5) HDMAMn (DMA Transfer Mode Setting Register)
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.
Transfer mode
7
HDMAM0
HDMAM1
HDMAM2
HDMAM3
HDMAM4
HDMAM5
(090CH)
(091CH)
(092CH)
(093CH)
(094CH)
(095CH)
[7:0]
6
Figure3.6.6 HDMAMn Register
HDMAMn Register
5
92CF26A-93
100: Source/destination INC
101: Source/destination DEC
110: Source/destination fixed
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
111: Reserved
DnM4
4
0
(MEM → MEM)
(MEM → MEM)
(I/O→ I/O)
DnM3
3
0
DnM2
(Note 2)
R/W
2
0
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
DnM1
1
0
TMP92CF26A
DnM0
2009-06-25
0
0