TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 533

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCP0 signal LCP0OC=1
LCP0 signal LCP0OC=0
LCDCTL0
(0285H)
LCDCTL1
(0286H)
LVSYNC
LHSYNC
LLOAD
LGOEn
LFR
All signal changes
LCP0P=0
LCP0P=1
bit Symbol
Read/Write
Reset State
Function
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
LD23-LD0
bit Symbol
Read/Write
Reset State
Function
LCP0
LCP0
<LCP0OC>=0, the LCP0 signal is always output. When <LCP0OC>=1, the LCP0
signal is output only when valid data is output.
LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When
The phase of the LCP0 signal can be inverted by the setting of LCDCTL1<LCP0P>.
PIP function
0:Disable
1:Enable
LCP0
phase
0: Rising
1: Falling
PIPE
LCP0P
7
0
7
1
Segment
data
0: Normal
1: Always
output “0”
LHSYNC
phase
0: Rising
1: Falling
ALL0
R/W
LHSP
6
0
6
0
LCD Control 0 Register
LCD Control 1 Register
R/W
Frame
divide
setting
0: Disable
1: Enable
92CF26A-531
LVSYNC
phase
0: Rising
1: Falling
FRMON
LVSP
5
0
5
1
Always
write “0”
LLOAD
phase
0: Rising
1: Falling
R/W
LLDP
4
−
0
4
0
3
3
FR signal
LCP0/Line
selection
0:Line
1:LCP0
DLS
2
2
0
LCP0(Note
0: Always
1: At valid
LLOAD
0: At setting
1: At valid
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
width
LCP0OC
LVSW1
output
data only
in register
data only
R/W
1
1
0
0
TMP92CF26A
R/W
2009-06-25
LCDC
operation
0: Stop
1: Start
LVSW0
START
0
0
0
0