TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 577

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDLDDLY<PDT> = 1
LLOAD
LCP0
LD17-LD0
3.19.6.1 Program example
LD17-LD0
LVSYNC
LHSYNC
LHSYNC
LGOE0
LLOAD
LGOE0
LFR
TFT-1(TFT panel: 320com × 240seg by H company)
ld
ld
ld
ld
ld
ld
ld
ld
ldw
ldw
ld
ld
ld
ld
ld
ld
ld
ldl
set
(lcdmode0),0bdh
(lcdmode1),00h
(lcdsize),84h
(lcdctl0),020h
(lcdctl1),0c1h
(lcdctl2),00h
(lcddvm0),01h
(lcddvm1),00h
(lcdhsp),278
(lcdvsp),326
(lcdhsdly),3
(lcdlddly),0a3h
(lcdo0dly),33
(lcdhsw),2
(lcdldw),100
(lcdho0w),99
(lcdhwb8),01h
(lsaml),400000
0,(lcdctl0)
3LCP0
1
33LCP0
35LCP0
2
92CF26A-575
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
3LCP0
3
259LCP0
1
101LCP0
PIP-OFF, Divide Frame ON: Line
LCP0 negedge, LHSYNC negedge, LVSYNC posedge, LLOAD
LHSYNC delay=3*LCP0
LLOAD delay=35*LCP0, <PDT>=1
LHSYNC enable width=259*LCP0
LLOAD enable width=101*LCP0
LCDC start
VRAM:SDRAM, f
320com,240seg
posedge
Divide Frame : Line=1
LHSYNC cycle(LCP0*208),valid data=120
LHSYNC cycle(LCP0*279
LVSYNC cycle(LHSYNC*327)
Frame Rate=12.5ns*16*279*327 (54Hz)
LGOE0 delay=33*LCP0
LGOE0 enable width=100*LCP0
<HSW8>=1
main area start address set
279LCP0
2
3
SYS
*16-clk, TFT256K color
240
3LCP0
327
TMP92CF26A
2009-06-25