TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 356

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDA pin
SCL pin
(6)
(7)
Start condition
Figure 3.15.10 Start condition generation and slave address generation
• Data with an addressing format is transferred
• A slave address with the same value that an I2CAR
• A GENERAL CALL is received (all 8-bit data are “0” after a start condition)
Clear the <TRX> to “0” for operation as a receiver.
master device is “1”, and is cleared to “0” by the hardware if the bit is “0”.
the <TRX> is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is
set to “1” by the hardware if it is “0”. When an Acknowledge signal is not returned, the
current condition is maintained.
The <TRX> is cleared to “0” by the hardware after a stop condition on the I2C bus is
detected or arbitration is lost.
SBIDBR are output on a bus after generating a start condition by writing “1” to the
SBICR2 <MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set “1” to <ACK> beforehand.
writing “1” to the <MST, TRX, PIN>, and “0” to the <BB>. Do not modify the contents
of <MST, TRX, BB, PIN> until a stop condition is generated on a bus.
SBISR<BB> will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
Transmitter/Receiver selection
Start/Stop condition generation
Set the SBICR2<TRX> to “1” for operating the TMP92CF26A as a transmitter.
In Slave Mode,
The <TRX> is set to “1” by the hardware if the direction bit (R/
In the Master Mode, after an Acknowledge signal is returned from the slave device,
When the SBISR<BB> is “0”, slave address and direction bit which are set to
When the <BB> is “1”, a sequence of generating a stop condition is started by
The state of the bus can be ascertained by reading the contents of SBISR<BB>.
A6
1
Figure 3.15.11 Stop condition generation
SDA pin
SCL pin
A5
2
92CF26A-354
Slave address and the direction bit
A4
3
A3
4
Stop condition
A2
5
A1
6
A0
7
R/ W
W
8
) sent from the
TMP92CF26A
Acknowledge
signal
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