TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 326

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SIOCLK
TXDCLK
Note1: The double buffer structure does not support SC0CR<RB8>.
Note2: If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2, the
(6) The Receiving Buffers
(7) Notes for Using Receive Interrupts
(8) Transmission counters
data may not be read properly. To avoid this situation, a read of receive buffer 2 should be triggered by a
receive interrupt.
structure.
Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register).
When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is
transferred to Receiving Buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be
generated. The CPU only reads Receiving Buffer 2 (SC0BUF). Even before the CPU
reads receiving Buffer 2 (SC0BUF), the received data can be stored in Receiving Buffer
1. However, unless Receiving Buffer 2 (SC0BUF) is read before all bits of the next data
are received by Receiving Buffer 1, an overrun error occurs. If an Overrun error occurs,
the contents of Receiving Buffer 1 will be lost, although the contents of Receiving
Buffer 2 and SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit - added in 8-Bit UART Mode - or the
most significant bit (MSB) - in 9-Bit UART Mode.
In 9-Bit UART Mode the wake-up function for the slave controller is enabled by setting
SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the value of
SC0CR<RB8> is 1.
like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is
generated every 16 SIOCLK clock pulses.
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• Receive interrupts can be detected either in level or edge mode. For details, see the
• When receive interrupts are set to level mode, once an interrupt occurs, the same
To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer
SIO interrupt mode is selectable by the register SIMC.
The transmission counter is a 4-bit binary counter used in UART Mode and which,
description of the SIO/SEI receive interrupt mode select register SIMC in the
section on interrupts.
interrupt will occur repeatedly even after control has jumped to the interrupt
routine unless interrupts are disabled.
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Figure 3.14.3 Generation of the transmission clock
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