TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 325

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(3) Serial clock generation circuit
(4) Receiving counter
(5) Receiving control
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each
data bit is sampled three times - on the 7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
This circuit generates the basic clock for transmitting and receiving data.
The receiving counter is a 4-bit binary counter used in UART Mode, which counts up
generated by dividing the output of the baud rate generator by 2, as described
previously.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the rising edge or falling
edge will be detected according to the setting of the SC0CR<SCLKS> register to
generate the basic clock.
clock, the internal clock f
external clock (SCLK0) is used to generate the basic clock SIOCLK.
sampled on the rising or falling edge of the shift clock which is output on the
SCLK0 pin, according to the SC0CR<SCLKS> setting.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the RXD0 signal is
sampled on the rising or falling edge of the SCLK0 input, according to the
SC0CR<SCLKS> setting
majority rule. Received bits are sampled three times; when two or more out of
three samples are 0, the bit is recognized as the start bit and the receiving
operation commences.
The values of the data bits that are received are also determined using the
majority rule.
• In I/O Interface Mode
• In UART Mode
• In I/O Interface Mode
• In UART Mode
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is
The SC0MOD0 <SC1:0> setting determines whether the baud rate generator
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the RXD0 signal is
The receiving control block has a circuit, which detects a start bit using the
92CF26A-323
IO
, the match detect signal from timer TMRA0 or the
TMP92CF26A
2009-06-25