TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 296

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(Value to be compared)
Match with TA0REG
Example: To output the following PWM waves on the TA1OUT pin (at f
X: Don't care, −: No change
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PM
PMFC
TA01RUN
Register buffer0
overflow is detected when the TA0REG double buffer is enabled.
2
n
To achieve a 20.48μs PWM cycle by setting φT1 to 0.16 μs (at f
20.48 μs ÷ 0.16 μs = 128
2
Therefore n should be set to 7.
Since the low level period is 16.0 μs when φT1 = 0.16 μs,
set the following value for TAREG:
TA0REG
In this mode the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
overflow
n
= 128
16.0 μs ÷ 0.16 μs = 100 = 64H
* Clock state
MSB
← −
← 1
← 0
← X
← −
← −
← 1
7
6
X
1
1
X
X
X
X
Figure 3.12.25 Register Buffer Operation
5
X
1
1
X
X
X
X
4
X
0
0
X
X
X
X
Up counter = Q
Clcok gear :
Prescaler of clock gear : 1/2
3
−
X
0
1
X
X
−
16.0 μs
20.48 μs
2
−
X
1
0
−
−
1
92CF26A-294
1
−
0
0
1
0
1
−
LSB
Q
1
1
0
0
1
0
X
X
X
1
Q
2
1/1
Stop TMRA0 and clear it to 0
Select 8-bit PWM mode (cycle: 2
input clock.
Write 64H.
Clear TA1FF to 0, enable the inversion and double buffer.
Set PM1 as the TA1OUT pin.
Start TMRA0 counting.
SYS
SYS
Shift into TA0REG(Register buffer0)
= 50 MHz).
= 50 MHz):
Up counter = Q
TA0REG (Register buffer0)
write
7
) and select φT1 as the
Q
2
TMP92CF26A
2
Q
3
2009-06-25
n