TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 74

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note1: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
Note2: Don’t start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that channel number is
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt
specified by micro DMA start vector” (in the Figure 3.5.1) and reading interrupt vector with setting below. The
vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And
INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
biggest (priority is lowest) is not started.(Because interrupt flag is cleared by micro DMA that priority is highest)
destination addresses are 32 bits wide, this type of register can only output 24-bit
addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a
32-bit address are not valid).
transfers and 4byte transfers. After a transfer in any mode, the transfer source and
transfer destination addresses will either be incremented or decremented, or will
remain unchanged. This simplifies the transfer of data from memory to memory, from
I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various
transfer modes, see section 3.5.2 (4) “Detailed description of the transfer mode
register”.
operations can be performed per interrupt source (Provided that the transfer counter
for the source is initially set to 0000H).
interrupts shown in the micro DMA start vectors in Table 3.5.1 and a micro DMA soft
start.
Destination Address INC Mode (micro DMA transfers are the same in every mode
except Counter Mode). (The conditions for this cycle are as follows: both source and
destination memory are internal-RAM and multiple of 4 numbered source and
destination addresses).
Although the control registers used for setting the transfer source and transfer
Three micro DMA transfer modes are supported: 1byte transfer, 2byte (One word)
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing
Micro DMA processing can be initiated by any one of 48 different interrupts – the 47
Figure 3.5.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer
States (1) and (2): Instruction fetch cycle (Prefetches the next instruction code)
State (3): Micro DMA read cycle.
State (4): Micro DMA writes cycle.
State (5): (The same as in state (1), (2).)
A23 to A0
Note: In fact, src and dst address are not outputted to A23-A0 pins
because they are internal RAM address.
f
Figure 3.5.2 Timing for micro DMA cycle
SYS
1 state
(1)
92CF26A-72
(2)
(3)
src
(4)
dst
(5)
TMP92CF26A
2009-06-25