TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 101

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.6.6
Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also possible
Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state.
Note 2: The transfer speed varies depending on the combination of source and destination.
Note 3: In the case of 0 waits
Read / Write
Read / Write
act as the bus master apart from the CPU. Therefore, care must be exercised to enable each
of these functions to operate smoothly.
transfer operation performed by the DMA controller is defined as “HDMA”, the display
RAM read operation performed by the LCD controller as “LDMA”, and the SDRAM auto
refresh operation performed by the SDRAM controller as “ARDMA”.
same time.
(1) CPU + HDMA
Considerations for Using More Than One Bus Master
CPU bus stop rate = t
HDMA start interval [s] = HDMA start interrupt period [s]
t
In the TMP92CF26A, the LCD controller, SDRAM controller, and DMA controller may
To facilitate explanation of DMA operation performed by each bus master, the DMA
The following explains various cases where two or more bus masters may operate at the
STOP
a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access) is
b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used.
to start HDMA by software.
the CPU and getting a bus acknowledgement. The DMA controller may be active while
the CPU is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere
with the CPU operation. However, if HDMA is started while the CPU is active, the CPU
cannot execute instructions while HDMA is being performed.
stop time (defined as “t
interval, and number of channels to be used.
possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4
states are needed at the end of each burst access.
The DMA controller performs DMA transfer (HDMA) after issuing a bus request to
Before activating the DMA controller, therefore, it is necessary to estimate the CPU
Read
Write
Read
Write
(HDMA) [s] = (Source read time + Destination write time) × Transfer count + α
Memory Type
I/O Type
Internal RAM
1 / 4
STOP
1 / 4
2 / 4
(Note 1)
I
2
−
S
STOP
(HDMA)[s] / HDMA start interval [s]
92CF26A-99
state/byte
state/byte
(HDMA)”) based on the transfer time, transfer start
1 word 6 / 2
1 word 3 / 2
Burst 1 / 2
Burst 1 / 2
External SDRAM
16-bit bus
NANDF
2 / 2
2 / 2
(Note 2)
(Note 2)
(Note 2)
(Note 2)
External SRAM
USB
2 / 2
2 / 2
2 / 2
2 / 2
16-bit bus
(Note 3)
(Note 3)
External SRAM
2 / 1
2 / 1
2 / 4
2 / 4
SPI
8-bit bus
TMP92CF26A
(Note 3)
(Note 3)
2009-06-25