TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 181

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.8.2
the necessary settings after reset.
･ Control registers: BnCSH/BnCSL(n = 0 to 3, EX)
･ Memory Start Address register: MSARn(n = 0 to 3)
･ Memory Address Mask register: MAMR (n = 0 to 3)
･ Page ROM Control register: PMEMCR
･Timing control registers: CSTMGCR, WRTMGCR, RDTMGCRn
･ On-chip Boot ROM Control register: BROMCR
(1) Control Registers
This section describes the registers to control the memory controller, their reset states and
Configures the basic settings of the memory controller, such as the memory type
specification and the number of wait states to be inserted into a read or write
cycle.
Specifies a start address fora selected address space.
Specifies a block size for a selected address space.
Selects a method of accessing Page-ROM.
Adjust the timing of rising and falling edges of control signals.
Selects a method of accessing Boot-ROM.
Control Rregisters and Memory Access Operations After Reset
The control registers of the memory controller are listed below.
92CF26A-179
TMP92CF26A
2009-06-25