TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 578

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDLDDLY<PDT> = 0
LLOAD
LCP0
LD17-LD0
LD17-LD0
LVSYNC
LHSYNC
LHSYNC
LLOAD
TFT-2(TFT panel: 240com x 320seg by SH company) (f
ld
ld
ld
ld
ld
ldw
ldw
ld
ld
ld
ld
ld
ld
ldl
set
(lcdmode0),3dh
(lcdmode1),00h
(lcdsize),75h
(lcdctl0),00h
(lcdctl1),061h
(lcdhsp),340
(lcdvsp),252
(lcdprvsp),7
(lcdhsdly),11
(lcdlddly),16
(lcdhsw),2
(lcdldw),64
(lcdhwb8),02h
(lsaml),400000h
0,(lcdctl0)
11LCP0
1
16LCP0
3LCP0
2
92CF26A-576
1
8
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
341LCP0
2
VRAM: In-RAM, f
320seg,240com
PIP-OFF, Divide Frame-OFF
LCP0 posedge, LHSYNC negedge, LVSYNC negedge, LLOAD
posedge
LVSYNC enable width=LHSYNC*2
LHSYNC cycle(LCP0*341)
LVSYNC cycle(LHSYNC*253)
Frame Rate=12.5ns*16*341*253 (58Hz)
Vertical front porch 7
LHSYNC delay=11*LCP0
LLOAD delay=16*LCP0 ,<PDT>=0
LHSYNC enable width=3*LCP0
LLOAD enable width=320*LCP0
<LDW8>=1
main area start address set
LCDC start
3
320LCP0
SYS
*16-clk, TFT256K color
SYS
=80MHz)
320
5LCP0
253
TMP92CF26A
2009-06-25
1