TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 450

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Transmitting number > payload × (number of available packet)
• Write number of payload × (number of available packet) in
• Total = Total − payload × (number of available packet)
relevant endpoint
If transmitting number reach to payload,
UDC sets 1 to relevant bit
of DATASET register.
B.
Figure 3.16.16 Transmitting Sequence in Dual Packet Mode
Data can be set to available FIFO when transmitting regardless of packet A or
Below is the Transmitting Sequence in Dual Packet Mode.
Wait transmitting event
When receiving In-Token from USB Host,
UDC transmits data.
Clear relevant bit of DATASET register
DATASETregister
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
92CF26A-448
data distinction
Transmittind
Transmitting number < payload × (number of available packet)
IDLE
• Write number of transmitting in relevant endpoint
• Total = 0
EOP register
Write 0 to only bit of relevant
endpoint
Transmitting event
Return to IDLE
• Accessing to EOP register is needed in
• Control transfer type is supported in
only single mode.
transmitting short packet.
UDC sets 1 to relevant bit
of DATASET register.
TMP92CF26A
2009-06-25