TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 551

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LHSYNC (Expansion)
LVSYNC
LHSYNC
LCP0
LFR
<FREDGE>=0
<FRMON> = 1
<FMP7:0> = N
<FML7:0> = M
<DLS> = 1
Note: prohibit to set <FREDGE>=1, always need to set <FREDGE>=0.
intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of “LCP0
× M”. The “M” value is specified in LCDDVM0<FMP7:4>.
When LCDCTL0<FRMON>= “1” and LCDCTL0<DLS>= “1”, frame output is inverted at
When <DLS>= “1” LFR signal synchronous with front edge of LHSYNC signal.
So, prohibit to set <FREDGE>= “1”, always need to set <FREDGE>= “0”.
N
M
M
92CF26A-549
TMP92CF26A
2009-06-25