TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 109

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

HDMATR
(097FH)
bit Symbol
Read/Write
Reset State
Function
Note: Read-modify-write instructions can be used on this register.
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
(256 × 7 × (1 / f
LHSYNC [period:s] = 54.95 [μs], it is assumed that HDMA transfer occurs once during
LHSYNC [period:s].
By writing “87H” to the HDMATR register, the maximum HDMA time is set to 29.9 [μs]
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
The time LDMA, ARDMA, and HDMA all occupy the bus is defined as:
Based on the above, the CPU bus stop rate is calculated as follows:
forcefully terminated at 29.9 [μs].
Timer
operation
0: Disable
1: Enable
t
t
CPU bus stop rate = t
STOP
STOP
DMATE
7
0
(ARDMA) = 2 / f
(LDMA･ARDMA･HDMA)
SYS
DMATR6
)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than
6
0
= (5.47 [μs] + 33.33 [ns]+ 29.9 [μs]) / 54.95 [μs] = 64.42 [%]
DMATR5
The value to be set in <DMATR6:0> should be obtained by
STOP
SYS
HDMATR Register
5
0
92CF26A-107
[Hz] = 33.33 [ns]
“Maximum bus occupancy time / (256/ f
(LDMA･ARDMA･HDMA) [s] / LHSYNC [period:s]
Maximum bus occupancy time setting
DMATR4
4
0
“00H” cannot be set.
R/W
DMATR3
3
0
DMATR2
2
0
SYS
DMATR1
)”.
1
0
TMP92CF26A
DMATR0
2009-06-25
0
0