TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 492

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Writing a 0 to the SPICT<TXE> bit during a transmission stops the transmission after
completing the transmission of the UNIT data currently being transmitted.
32 bytes. The TEND interrupt is generated upon completion of the transmission of the last
UNIT data.
The state of the SPICT<TXE> bit can be changed even during the data transmission.
The TEMP interrupt is generated when the empty space size of the FIFO becomes 16 or
92CF26A-490
TMP92CF26A
2009-06-25