TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 27

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PLLCR1
(10E9H)
PLLCR0
(10E8H)
PxDR
(xxxxH)
bit symbol
Read/Write
Reset State
Function
bit symbol
Read/Write
Reset State
Function
bit symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: “n” in PxnD denotes the bit number of PORTx.
(Purpose and using)
•
•
•
•
•
•
The Output/Input buffer control table is shown below.
PLL0 for
CPU
0: Off
1: On
This register is used to set each pin-status at stand-by mode.
All ports have registers of the format shown above. (“x” indicates the port name.)
For each register, refer to 3.5 Function of Ports.
Before “HALT” instruction is executed, set each register pin-status. They will be
This is the case regardless of stand-by modes (IDLE2, IDLE1 or STOP).
This is the case regardless of using PMC function. For details, refer to PMC
Px7D
effective after the CPU has executes the “HALT” instruction.
section.
PLL0
7
7
7
0
1
−
OE
0
0
1
1
Select
fc-clock
0 : f
1 : f
PLL1 for
USB
0: Off
1: On
PxnD
FCSEL
Px6D
PLL1
R/W
R/W
OSCH
PLL
0
1
0
1
6
6
6
−
0
0
1
Figure 3.3.6 SFR for Drive register
Output/Input buffer drive-register for standby-mode
Output buffer
Lock-up
timer
Status flag
Select
stage of
Lock up
counter
0: 12 stage
1:13 stage
(for PLL1)
0 : not end
1 : end
Figure 3.3.5 SFR for PLL
LUPSEL
LUPFG
(for PLL0)
Px5D
R
5
5
5
0
0
1
−
OFF
OFF
OFF
ON
92CF26A-25
Px4D
4
4
4
1
−
Input buffer
R/W
OFF
OFF
OFF
ON
Px3D
3
3
3
1
−
Px2D
2
2
−
2
1
Px1D
1
1
1
−
1
PLLTIMES
Select the
number of
PLL
0: × 12
1: × 16
TMP92CF26A
Px0D
R/W
0
0
0
1
−
0
2009-06-25