TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 266

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: In case of LB type NANDF, programming page size is normally each 2112 bytes and ECC calculation is
processed each 518 (512) bytes. Please take care of programming flow. In details, refer the NANDF memory
specifications.
Writing ECC to NAND Flash
; ***** Write dummy data & ECC *****
;
; ***** Set auto page program*****
;
;
;
;
;
; ***** Read status*****
;
;
;
;
;
;
;
;
Executing page program
Reading status
ldw
ldw
ldw
ldw
ldw
ldw
The write operation is repeated four times to write 2112 bytes.
ldw
ldw
ldw
Wait set up time (from Busy to Ready)
ldw
ldw
ldw
ldw
(ndfmcr0),5088h ; ECC circuit disable, data write mode
(ndfdtr0),xxxxh
Write to 207-206hex address:
(ndfdtr1),xxxxh
Write to 209-208hex address:
(ndfdtr0),xxxxh
Write to 20B-20Ahex address:
(ndfdtr1),xxxxh
Write to 20D-20Chex address:
(ndfdtr0),xxxxh
Write to 20F-20Ehex address:
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0010h
(ndfmcr0),5008h ; WE disable, CLE disable
1. Flag polling
2. Interrupt
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0070h
(ndfmcr0),5008h ; WE disable, CLE disable
xxxx,(ndfdtr0)
92CF26A-264
; Redundancy area data write
; Redundancy area data write
; Redundancy area data write
; Redundancy area data write
; Redundancy area data write
; Auto page program command
; Status read command
; Status read
> D79-64
> D63-48
> D47-32
> D31-16
> D15-0
TMP92CF26A
2009-06-25