TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 630

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.24.2
WDT counter
WDT interrupt
WDT clear
(Soft ware)
WDT counter
WDT interrupt
Internal reset
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
reset.
continues counting during bus release (when
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
input clock. The binary counter can output 2
Figure 3.24.3. After a reset, the clock f
dividing the high-speed oscillator clock (f
Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
The watchdog timer begins operating immediately on release of the watchdog timer
The watchdog timer is halted in IDLE1 or STOP mode. The watchdog timer counter
When the device is in IDLE2 mode, the operation of WDT depends on the
The watchdog timer consists of a 22-stage binary counter which uses the clock (f
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be 32 clocks (102.4 μs at f
n
n
Figure 3.24.2 Normal Mode
Figure 3.24.3 Reset Mode
Overflow
92CF26A-628
32 clocks (102.4 μs at f
Overflow
IO
OSCH
is divided f
15
BUSAK
/f
) by sixteen through the clock gear function.
IO
, 2
17
SYS
OSCH
/f
Write clear code
goes low).
IO
by two, where f
, 2
= 10 MHz)
19
/f
OSCH
IO
and 2
= 10 MHz) as shown in
21
SYS
/f
IO
.
is generated by
TMP92CF26A
2009-06-25
0
IO
) as the