TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 615

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADREG1L
(12A2H)
ADREG1H
(12A3H)
ADREG0H
(12A1H)
ADREG0L
(12A0H)
•
•
•
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
“1”. When Lower register (ADRECxL) is read, this bit is cleared to “0”.
ADREGxH/L before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Channel X conversion
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the
result
Store Lower 2 bits of
Store Lower 2 bits of
ADR01
ADR09
ADR11
ADR19
AN0 AD conversion
AN1 AD conversion
7
7
7
7
0
0
0
0
result
result
R
R
Figure 3.23.6 AD Conversion Registers
AD Conversion Result Register 0 High
AD Conversion Result Register 1 High
AD Conversion Result Register 0 Low
AD Conversion Result Register 1 Low
ADREGxH
ADR10
ADR00
ADR08
ADR18
9
6
6
6
6
7
0
0
0
0
8
6
7
Store Upper 8 bits of AN0 AD conversion result
Store Upper 8 bits of AN1 AD conversion result
5
92CF26A-613
ADR07
ADR17
5
5
5
5
0
0
4
6
3
5
ADR06
ADR16
2
4
4
4
4
4
0
0
1
3
R
R
0
2
ADR05
ADR15
3
3
3
3
0
0
1
7
0
6
ADR04
ADR14
5
2
2
2
2
0
0
4
0:No
0:No
3
Overrun
flag
1: Generate
Overrun
flag
1: Generate
generate
generate
ADR13
ADR03
OVR0
OVR1
1
1
2
0
1
0
1
0
0
ADREGxL
1
TMP92CF26A
R
R
AD
conversion
result store
flag
1: Stored
AD
conversion
result store
flag
1: Stored
2009-06-25
ADR0RF
ADR1RF
0
ADR02
ADR12
0
0
0
0
0
0
0
0