TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 293

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TA0REG-WR
TA01RUN<TA0RDE>
(Value to be compared)
Note: The values that can be set in TAxREG renge from 01h to 00h (equivalent to 100h). If the maximum value 00h is
Match with TA0REG
Match with TA1REG
TA0IN
TA01MOD<TA0CLK1:0>
φT16
Selector
φT1
φT4
set , the match-detect signal goes active when the up-counter overfolws.
and up counter
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
TA01RUN<TA1RUN> should be set to 1 so that UC1 is set for counting.
will be shifted into TA0REG each time TA1REG matches UC0.
varied).
Register buffer
In this mode a programmable square wave is generated by inverting the timer
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
Figure 3.12.21 shows a block diagram representing this mode.
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
Use of the double buffer facilitates the handling of low-duty waves (when duty is
TA0REG
Figure 3.12.21 Block Diagram of 8-Bit PPG Output Mode
Selector
Shift trigger
Register buffer
Figure 3.12.22 Operation of Register Buffer
Comparator
TA0REG
Internal data bus
(Up counter = Q
up counter
(UC0)
92CF26A-291
8-bit
Q
1
Comparator
1
TA1REG
)
Q
2
TA01RUN<TA0RUN>
(Up counter = Q
Shift from register buffer
TA1OUT
TA1FF
2
)
Q
Inversion
2
TA0REG (Register buffer)
write
Q
INTTA0
INTTA1
3
TA1FFCR<TA1FFIE>
TMP92CF26A
2009-06-25