TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 547

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDHO2W
(0298H)
LCDHO1W
(0297H)
LCDHO0W
(0296H)
LCDHWB8
(0299H)
Signal Name
LCP0
LGOE0 signal
LGOE1 signal
LGOE2 signal
(4) LGOE0 to LGOE2 Signals
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
signal. For these signals, the enable width, delay time, and phase timing can be adjusted as
shown below.
The LCDC has three signals (LGOE0 to LGOE2) that can be controlled like the LHSYNC
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
O0W7
O1W7
O2W7
O2W9
7
0
7
0
7
0
7
0
High width setting
LGOE0: LCP0 clock = 1, 2, 3 … 512 pulses
LGOE1: LCP0 clock = 1, 2, 3 … 1024 pulses
LGOE2: LCP0 clock = 1, 2, 3 … 1024 pulses
O0W6
O1W6
O2W6
O2W8
6
6
6
0
0
0
6
0
Signal width Bit8,9 Register
LGOE0 width Register
LGOE1 width Register
LGOE2 width Register
92CF26A-545
O0W5
O1W5
O2W5
O1W9
5
5
5
5
0
0
0
0
LGOE0 width (bits 7-0)
LGOE1 width (bits 7-0)
LGOE2 width (bits 7-0)
O0W4
O1W4
O2W4
O1W8
4
0
4
0
4
0
4
0
W
W
W
W
width (bit 8)
LGOE0
O0W3
O1W3
O2W3
O0W8
3
3
3
0
0
0
3
0
LLOAD width (bits 9-8)
O0W2
O1W2
O2W2
LDW9
2
2
2
0
0
0
2
0
O0W1
O1W1
O2W1
LDW8
1
0
1
0
1
0
1
0
TMP92CF26A
width (bit 8)
2009-06-25
LHSYNC
O0W0
O1W0
O2W0
HSW8
0
0
0
0
0
0
0
0