TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 35

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PxDR
(xxxxH)
3.3.6
bit symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: “n” in PxnD denotes the bit number of PORTx.
Standby controller
(1) HALT Modes and Port Drive-register
(Purpose and using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this registers of the format shown above (“x” indicates the port-name.)
• For each register, refer to 3.5 Function of Ports.
• Before “HALT” instruction is executed, set each register pin-status. They will be
• This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP).
• This is the case regardless of using PMC function. For details, refer to PMC section.
IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0>
register and each pin-status is set according to the PxDR register, as shown below.
effective after the CPU has executed the “HALT” instruction.
When the HALT instruction is executed, the operating mode switches to IDLE2,
The Output/Input-buffer control table is shown below.
The subsequent actions performed in each mode are as follows:
Px7D
7
1
−
OE
0
0
1
1
a. IDLE2: Only the CPU halts.
b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to
c. STOP: All internal circuits stop operating.
Table 3.3.3 SFR setting operation during IDLE2 mode
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.3.3 shows the registers setting operation during IDLE2 mode.
PxnD
Px6D
0
1
0
1
6
−
1
operate.
Internal I/O
A/D converter
TMRA01
TMRA23
TMRA45
TMRA67
TMRB0
TMRB1
SIO0
WDT
SBI
Output/Input buffer drive-register for standby-mode
Output buffer
Px5D
5
1
−
OFF
OFF
OFF
ON
92CF26A-33
Px4D
4
1
−
Input buffer
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TA45RUN<I2TA45>
TA67RUN<I2TA67>
R/W
WDMOD<I2WDT>
SC0MOD1<I2S0>
TB0RUN<I2TB0>
TB1RUN<I2TB1>
ADMOD1<I2AD>
SBIBR0<I2SBI>
OFF
OFF
OFF
ON
Px3D
SFR
3
1
−
Px2D
−
2
1
Px1D
1
−
1
TMP92CF26A
Px0D
0
1
−
2009-06-25