TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 411

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Descriptor RAM
(0500H)
(067FH)
Set Descriptor
STALL
(07E8H)
bit Symbol
Read/Write
Reset State
3.16.3.28 Set Descriptor STALL Register
3.16.3.29 Descriptor RAM Register
bit Symbol
Read/Write
Reset State
Bit0: S_D_STALL
0: Software control (Default)
1: Automatically STALL
stage for Set Descriptor Request.
bytes. However, when storing descriptor, write according to descriptor RAM structure
sample.
processing of SET_DESCRIPTOR request.
register.
request in the following sequence.
connect to the host, executing INIT_DESCRIPTOR command is not necessary.
This register sets whether returns STALL automatically in data stage or status
This register is used for store descriptor to RAM. The size of the descriptor is 384
Read/Write timing is only possible before detection of USB_RESET or during
SET_DESCRIPTOR request processes from INT_SETUP assert until access of EOP
If there is rewriting request of descriptor in SET_DESCRIPTOR, process the
If USB_RESET is detected, it starts reading automatically. Therefore, when it
Undefined
1)
2)
3)
4)
5)
R/W
D7
7
7
Read every packet of the descriptor that is transferred by SET_DESCRIPTOR
requests every packet.
When reading descriptor number of last packet finished, write all descriptors
to RAM for descriptor.
When writing is completed, execute INIT_DESCRIPTOR of COMMAND
register.
When all the process is completed, access EOP register, and finish status
stage.
When INT_STAS is received, it shows normal finish of status stage.
Undefined
R/W
D6
6
6
Undefined
92CF26A-409
R/W
D5
5
5
Undefined
R/W
D4
4
4
Undefined
R/W
3
D3
3
Undefined
2
R/W
D2
2
Undefined
1
R/W
D1
TMP92CF26A
1
2009-06-25
S_D_STALL
Undefined
W
0
0
R/W
D0
0