TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 290

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Up
counter
Comparator output
(Match detect)
<TA01RUN>
Comparator
Example: To output a 3.2μs square wave pulse from the TA1OUT pin at f
X: Don’t care, −: No change
Bit7 to Bit2
TA01RUN
TA01MOD
TA1REG
TA1FFCR
PM
PMFC
TA01RUN
UC1 clear
TA01RUN
TA1OUT
INTTA1
TA1FF
timing
Bit1
Bit0
φT1
b.
make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be
used.
Figure 3.12.17 Square Wave Output Timing Chart (50% duty)
status output via the timer output pin (TA1OUT).
* Clock state
Generating a 50% duty ratio square wave pulse
← −
← 0
← 0
← X
← −
← −
← −
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its
0
7
X
X
X
X
X
0
0
6
1
X
X
X
X
X
X
0
5
X
X
X
X
X
X
0
4
Clcok gear :
Prescaler of clock gear : 1/2
2
−
0
1
1
X
X
−
3
2
−
1
0
0
−
−
1
92CF26A-288
3
X
0
1
1
0
1
1
1
0
X
X
X
−
0
1
−
0
1.6 μs at f
1
1/1
Stop TMRA1 and clear it to “0”.
Set the timer register to 3.2 μs ÷ φT1 ÷ 2 = 0AH
Clear TA1FF to “0” and set it to invert on the match detect
signal from TMRA1.
Set PM1 to function as the TA1OUT pin.
Start TMRA1 counting.
Select 8-bit timer mode and select φT1 (0.16 μs at f
50 MHz) as the input clock.
C
2
= 50 MHz
3
SYS
0
= 50 MHz, use the following procedure to
1
2
3
TMP92CF26A
0
2009-06-25
SYS
=