TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 499

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SPITD0
(830H)
(831H)
SPITD1
(832H)
(833H)
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Transmit Data
1-byte write
2-byte write
4-byte write
Write Size
○: All data that are written by the CPU are transmitted.
• : Invalid data are also transmitted along with the data written by the CPU.
last-written data is read out. This register is overwritten if the next data is written with the
transmit FIFO being full.
operations that are performed by using four-byte instructions, such as the parallel
operation of the SPI and DMA.
be written.
For more details, please refer to the following table.
(5) SPI Transmit Data Register (SPITD)
The SPITD0 and SPITD1 registers are used for writing the transmit data.
This register is used for writing the transmit data. When this register is read, the
Since the transmit data registers can contain data of up to four bytes, it can support write
When writing the data, the transmit data at the address 830 must always be the first to
There are several restrictions of the data writing methods (i.e., instructions to be used).
TXD15
TXD15
TXD7
TXD7
15
15
7
7
ld (0x830),a
ld (0x830),wa
ld (0x830),xwa
0
0
0
0
Instruction
Example
TXD14
TXD14
TXD6
TXD6
14
14
6
6
0
0
0
0
Figure 3.17.12 SPITD Register
transmission
unit16 = 0
TXD13
TXD13
TXD5
TXD5
UNIT-mode Transmission
1-byte
13
13
5
5
0
0
0
0
SPITD0 Register
SPITD1 Register
○
•
•
92CF26A-497
(FIFO Disabled)
Transmit data bits [15:8]
Transmit data bits [15:8]
Transmit data bits [7:0]
Transmit data bits [7:0]
TXD12
TXD12
TXD4
TXD4
12
12
4
4
0
0
0
0
transmission
unit16 = 1
2-byte
R/W
R/W
R/W
R/W
○
•
•
TXD11
TXD11
TXD3
TXD3
11
11
3
0
3
0
0
0
transmission
Sequential-mode Transmission
Prohibited
unit16 = 0
TXD10
TXD10
TXD2
TXD2
1-byte
10
10
2
0
0
2
0
0
○
○
(FIFO Enabled)
TXD1
TXD9
TXD1
TXD9
1
9
0
0
1
9
0
0
transmission
unit16 = 1
2-byte
○
○
•
TMP92CF26A
TXD0
TXD8
TXD0
TXD8
2009-06-25
0
8
0
0
0
8
0
0