TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 240

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.10.4
Please carefully read the following to ensure proper use of the SDRAMC.
This section describes the points that must be taken into account when using the SDRAMC.
1) WAIT access
2) Execution of the Self Refresh Entry, Initialization Sequence, or Precharge All command
3) Auto Refresh interval setting
4) Changing SFR settings
5) Disabling the SDRAMC
6) Using LCDC, DMAC with SDRAMC
Considerations for Using the SDRAMC
LOOP:
before the HALT instruction
than the SDRAM.
external WAIT period that can be set is limited to “Auto Refresh interval × 8190”.
Initialization Sequence, Precharge All) requires several states after the SDCMM
register is set.
insert at least 10 bytes of NOP or other instructions.
minimum operation frequency and minimum Auto Refresh interval of the SDRAM to
be used.
Refresh interval must be set carefully.
disable the Auto Refresh function.
that the SDRAMC is disabled (SDACR<SMAC> =“0”).
condition, there is one limitation. When SDRAM is set as VRAM for LCD controller and
DMA controller is operated at the same time, always set to “1” to SDACR<SPRE>.
When SDRAM is used, the following restriction applies to memory access to other
In the external WAIT pin input setting of the memory controller, the maximum
Execution of the commands issued by the SDRAMC (Self Refresh Entry,
Therefore, to execute the HALT instruction after one of these commands, be sure to
When SDRAM is used, the system clock frequency must be set to satisfy the
In a system in which SDRAM is used and the clock is geared up and down, the Auto
Before changing the Auto Refresh interval, ensure that SDRCR<SRC> is set to “0” to
Before changing the settings of the SDACR<SPRE> and SDCISR registers, ensure
Set the following procedure, when disable the SDRAMC.
And this micro has LCD controller and DMA controller, in case of using below
LD
LD
CP
JP
LD
(SDCMM),0x02
A,(SDCMM)
A,0x00
NZ,LOOP
(SDACR),0x00
92CF26A-238
;
;
;
;
;
Issue to All Bank Precharge
Read SDCMM
Palling it until the All Bank Precharge command is finished
Stop the SDRAM controller
TMP92CF26A
2009-06-25