TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 754

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
SBIDBR
SBICR1
SBICR2
SBIBR0
SBICR0
I2CAR
SBISR
When
When
write
read
(17) SBI
Serial bus
interface
control
register 1
SBI
buffer
register
I
Address
register
Serial bus
interface
status
register
Serial bus
interface
control
register 2
Serial bus
interface
baud rate
register 0
Serial bus
interface
control
register 0
2
C BUS
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
1240H
1241H
1242H
1243H
1244H
1247H
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
Number of transfer bits
000: 8
011: 3
110: 6
Master/
Slave
status
monitor
0:Slave
1:Master
Always
read “0”
SBI
operation
0:disable
1:enable
SBIEN
MST
BC2
DB7
R/W
R/W
SA6
W
7
0
0
0
−
0
0
001: 1
100: 4
111: 7
Transmitter/
Receiver
status
monitor
0:Receiver
1:Transmit-
IDLE2
0: Stop
1: Operate
ter
I2SBI
R/W
BC1
DB6
TRX
R/W
R/W
SA5
6
0
0
0
0
−
0
92CF26A-752
010: 2
101: 5
I
status
monitor
0: Free
1: Busy
Start/Stop
condition
0: Stop
1: Busy
2
C bus
condition
condition
BC0
DB5
R/W
SA4
BB
5
0
0
0
−
1
−
0
Slave Address setting
Acknowledge
mode
specification
0: Disable
1: Enable
INTSBI
request
monitor
0: Request
1: Cancel
Cancel
INTSBI
interrupt
request
0:Don’t
1:Cancel
R (receive)/W (Transmit)
care
interrupt
request
ACK
R/W
DB4
SA3
R/W
PIN
4
0
0
1
−
1
−
0
Undefined
Always read as “1”.
Always read as “0”.
R/W
Always
read as “1”.
Arbitration
lost
detection
monitor
0: −
1: Detected
Serial bus interface
operation mode
selection
00: Port mode
01: (Reserved)
10: I
11: (Reserved)
AL/SBIM1 AAS/SBIM0
DB3
SA2
R/W
2
3
R
−
1
0
0
C bus mode
−
1
−
0
R
R
Setting for the divisor value “n”
(When writing)
000: 4
011: 7
110: 10
Slave
Address
match
detection
monitor
0:
Undetected
1: Detected
SCK2
DB2
SA1
R/W
2
0
0
0
−
1
−
0
R/W
001: 5
100:8
111: (Reserved)
General
call
detection
monitor
0:
Undetected
1: Detected
Software reset generate
write “10” and “01”, then
an internal reset signal is
generated.
SWRST1
SCK1
DB1
AD0/
SA0
R/W
1
0
0
TMP92CF26A
0
−
1
−
0
2009-06-25
010: 6
101: 9
Address
recognition
0: Enable
1: Disable
Last
receive bit
monitor
0: “0”
1: “1”
Always
write “0”.
/SWRMON
SWRST0
SCK0
LRB/
R/W
DB0
ALS
R/W
R/W
0/1
0
0
0
−
0
−
0