TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet

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... TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company ...

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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Preface ...

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Outline and Features The TMP92CF26A is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CF26AXBG is housed in a 228-pin BGA package. (1) CPU: 32-bit CPU (High-speed 900/H1 CPU) • Compatible with TLCS-900/L1 ...

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USB (universal serial bus) controller: 1 channel • Supports USB (ver.1.1) • Full-speed (12 Mbps) (Low-speed is not supported.) • Endpoint 0: Control 64 bytes × 1 FIFO Endpoint 1: BULK (output) 64 bytes × 2 FIFOs Endpoint 2: ...

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Interrupts: 56 interrupts • 9 CPU interrupts: Software interrupt instruction and illegal instruction • 38 internal interrupts: Seven selectable priority levels • 9 external interrupts: Seven selectable priority levels (8-edge selectable) (22) DMAC function: 6 channels • High-speed data ...

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AN1)PG0 to PG1 10-bit 6ch (AN2, MX)PG2 AD (AN3, MY, ADTRG )PG3 Converter (AN4 to AN5)PG4 to PG5 AVCC, AVSS VREFH, VREFL Touch Screen (PX, INT4)P96 I/F (PY)P97 (TSI) (TXD0)P90 SERIAL I/O (RXD0)P91 SIO0 (CTS0, SCLK0)P92 (I2S0CKO)PF0 2 ...

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Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CF26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CF26A ...

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Ball Ball Pin name No. No. A1 Dummy1 D9 A2 PG2,AN2, MX D10 A3 PA6,KI6 D11 A4 PA5,KI5 D12 A5 PA3,KI3 D13 A6 PA1,KI1 D15 A7 DVCC1A5 D16 A8 PF1,I2S0DO D17 A9 PJ6,NDCLE E1 PJ1, SDCAS , SRLUB A10 E2 ...

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Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Number Pin name I/O of Pins I/O P10 to P17 I/O 8 ...

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Table 2.2.1 Pin names and functions (2/6) Number Pin name I/O of Pins P86 Output CSZD 1 Output Output P87 Output CSXB 1 Output Output P90 I/O 1 TXD0 Output P91 I/O 1 RXD0 ...

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Table 2.2.1 Pin names and functions (3/6) Number Pin name I/O of Pins PF0 I/O 1 I2S0CKO Output PF1 I/O 1 I2S0DO Output PF2 I/O 1 I2S0WS Output PF3 I/O 1 I2S0WS Output PF4 I/O 1 I2S1CKO Output PF5 I/O ...

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Table 2.2.1 Pin names and functions (4/6) Number Pin name I/O of Pins PK0 Output 1 LCP0 Output PK1 Output 1 LLOAD Output PK2 Output 1 LFR Output PK3 Output 1 LVSYNC Output PK4 Output 1 LHSYNC Input PK5 Output ...

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Number Pin name I/O of Pins PR3 I/O 1 SPCLK Output PT0 to PT7 I/O 8 LD8 to LD15 Output PU0 to PU4,PU6 I/O 6 Output LD16 to LD20,LD22 PU5 I/O 1 LD21 Output PU7 I/O LD23 1 Output EO_TRGOUT ...

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Table 2.2.1 Pin names and functions (6/6) Number Pin name I/O of Pins D+, D− 2 I/O CLKOUT 1 Output AM1,AM0 2 Input DBGE 1 Input X1/X2 2 I/O XT1/XT2 2 I/O RESET 1 Input VREFH 1 Input VREFL 1 ...

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Operation This section describes the basic components, functions and operation of the TMP92CF26A. 3.1 CPU The TMP92CF26A contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the ...

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Reset Operation When resetting the TMP92CF26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the X1=10MHz). At reset, since the clock doublers (PLL0) is ...

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Read Figure 3.1.1 TMP92CF26A Reset timing chart 92CF26A-15 TMP92CF26A Write 2009-06-25 ...

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This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. When Powering on DVCC1A 1.5V DVCC1B Power DVCC1C 1.5-V rails should be turned on first, followed by ...

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Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin AM1 AM0 RESET ...

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Memory Map Figure 3.2 memory map of the TMP92CF26A. 000000H 000100H 001FF0H 002000H 010000H 021FFFH 046000H (Internal Back Up RAM 16kbyte) 04A000H External memory F00000H Provisional Emulator Control Area F10000H External memory FFFF00H Vector table (256 Byte) ...

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Clock Function and Standby Function The TMP92CF26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise reduction circuits. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram ...

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The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. instruction IDLE2 mode interrupt (I/O operate) instruction IDLE1 mode interrupt (Operate only oscillator) ...

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Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> (High/Low frequency oscillator circuit) SYSCR0<XTEN > PLLCR1<PLLON>, PLLCR0<LUPFG> XT1 Low frequency fs Oscillator circuit XT2 C lock Doubler0 (PLL0) × (12 or16 igh frequency Oscillator circuit f X2 OSCH Clock ...

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TMP92CF26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator 10MHz. Don’t connect oscillator more than 10MHz. When clock is input ...

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SFR 7 SYSCR0 bit Symbol (10E0H) Read/write Reset State Function Low -frequency oscillator circuit (fs) 0: Stop 1: Oscillation 7 SYSCR1 bit Symbol (10E1H) Read/write Reset State Function 7 – SYSCR2 bit Symbol (10E2H) Read/write Reset State 0 Function ...

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EMCCR0 Bit symbol PROTECT (10E3H) R Read/Write Reset State 0 Function Protect flag 0: OFF 1: ON EMCCR1 Bit symbol (10E4H) Read/Write Reset State Function EMCCR2 Bit symbol (10E5H) Read/Write Reset State Function Note: In case restarting the oscillator ...

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PLLCR0 bit symbol (10E8H) Read/Write Reset State Function Select fc-clock Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. 7 PLL0 PLLCR1 bit symbol (10E9H) Read/Write 0 Reset State Function ...

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System clock controller The system clock controller generates the system clock signal (f internal I/O. SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator. SYSCR1<GEAR2:0> sets the high frequency clock gear to either ...

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Clock doubler (PLL) PLL0 outputs the f PLL frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, so setting to PLLCR0 and PLLCR1-register is needed before ...

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The following is an example of settings for PLL0-starting and PLL0 stopping. (Example-1) PLL0-starting PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LD (PLLCR1),1XXXXXXXXB LUP: BIT 5,(PLLCR0) JR Z,LUP LD (PLLCR0), X1XXXXXXB X: Don't care <PLL0> <FCSEL> PLL output: f PLL Lockup ...

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Limitations on the use of PLL0 1. When stopping PLL operation during PLL0 use, execute the following settings in the same order. LD (PLLCR0),X0XXXXXXB LD (PLLCR1),0XXXXXXXB X: Don't care 2. When shifting to STOP mode during PLL use, execute the ...

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Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) Runaway prevention ...

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Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonator C2 XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 ...

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Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or ...

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Standby controller (1) HALT Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0> register and each pin-status is set ...

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The operation of each of the different Halt Modes is described in Table 3.3.4. Table 3.3.4 I/O operation during Halt Modes HALT Mode SYSCR2 <HALTM1:0> CPU, MAC I/O ports TMRA, TMRB SIO,SBI A/D converter Block WDT I2S, LCDC, SDRAMC, Interrupt ...

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Table 3.3.5 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt HALT mode INTWDT INT0 to 5 (Note1) INTKEY INTUSB INT6 to 7(PORT) (Note1) INT6 to 7(TMRB) INTALM, INTRTC INTTA0 to 7, INTTP0 INTTB00 to 01, ...

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IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H LD (PCFC), 02H 8203H LD (IIMC0), 00H 8206H LD (INTE0), 06H 8209H EI 5 820BH LD (SYSCR2), 28H 820EH ...

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Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of ...

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STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure ...

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Input Function Port Name Name During Reset D0-D7 D0-D7 OFF 16bit Start OFF P10-P17 D8-D15 Boot Start ON 16bit Start OFF − P60-P67 Boot Start ON − P71-P74 P75 NDR/ W P76 WAIT − P90 P91 RXD0 P92 ,SCLK0 CTS ...

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Output Function Port Name Name During Reset D0-7 D0-D7 OFF 16bit Start OFF P10-17 D8-D15 Boot Start OFF P40-P47 A0-A7 ON P50-P57 A8-A15 16bit Start ON P60-67 A16-A23 Boot Start OFF P70 ON RD P71 , WRLL NDRE P72 , ...

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Output Function Port Name During Name Reset PM1 MLDALM,TA1OUT ON PM2 , MLDALM ALARM PM7 PWE PN0-PN7 KO0-KO7 PP1 TA3OUT OFF PP2 TA5OUT PP3 TA7OUT − PP4-PP5 PP6 TB0OUT0 ON PP7 TB1OUT0 − PR0 PR1 SPDO PR2 SPCS PR3 SPCLK ...

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Boot ROM The TMP92CF26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CF26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according ...

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Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CF26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MULTI mode, ...

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Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless ...

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Work Area for Boot Program (4 Kbytes) 003000H Download Area for User Program (124 Kbytes) 021FFFH 046000H Work Area for User Program (14 Kbytes) 049800H Stack Area for Boot program (2K bytes) 049FFFH Figure 3.4.3 How the Boot Program ...

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Port settings Table 3.4.3 shows the port settings by the boot program. When designing your application system, please also refer to Table 3.4.4 for recommended pin connections for using the boot program. The boot program only sets the ports ...

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Table 3.4.4 Recommended Pin Connections Recommended Pin Connections for Each Download Function Port Name I/O Name UART P90 TXD0 Output Connect to the level shifter. P91 RXD0 Input −−− USB D+ I/O No special setting is needed for booting via ...

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I/O register settings Table 3.4.5 shows the I/O registers that are set by the boot program. After the boot sequence, if execution moves to an application system program without a reset being asserted, the settings of these I/O registers ...

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Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory). Level PC Shifter Note: When USB ...

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UART data transfer format Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud rate modification command, operation command, and version management information, respectively. Please also refer to the description of boot program operation later in ...

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Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) 9600 Modification Command 28H Note (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. OSCH Note (oscillation frequency) is 6.00, 8.00, or ...

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The receive data in the 8th byte is baud rate modification data. The five kinds of baud rate modification data shown in Table 3.4.8 are available. Even when the baud rate is not changed, the initial baud rate data ...

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Error codes The boot program uses the error codes shown in Table 3.4.12 to notify the PC of its processing status. Table 3.4.12 Error Codes Error Code 62H Unsupported baud rate 64H Invalid operation command A1H Framing error in ...

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Notes on Intel Hex format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it ...

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User program receive error If either of the following error conditions occurs while a user program is being received, the boot program stops operation. If the record type is other than 00H, 01H, or 02H If a checksum error ...

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Others a) Handshake function Although the pin is available in the TMP92CF26A, the boot program does CTS not use it for transfer control. b) RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program ...

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Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). PUCTL R4 = 100 kΩ R1 ...

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The following shows an overview of the USB communication flow. Host (PC) Send GET_DISCRIPTOR Connection Recognition Send DESCRIPTOR information Send the microcontroller information command Send microcontroller information data Check data Data Transfer Send the microcontroller information command Convert Intel Hex ...

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Table 3.4.15 Vendor Request Commands Command Name Value of bRequest Microcontroller information 00H command User program transfer start 02H command User program transfer result 04H command Table 3.4.16 Setup Command Data Structure Field Name Value bmRequestType 40H bRequest 00H, 02H, ...

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Table 3.4.17 Standard Request Commands Standard Request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR SET_DISCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME Table 3.4.18 Information Returned by GET_DISCRIPTOR DeviceDescriptor Field Name Blength 12H BdescriptorType 01H BcdUSB 0110H BdeviceClass 00H BdeviceSubClass 00H BdeviceProtocol 00H BmaxPacketSize0 ...

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ConfigrationDescriptor Field Name bLength 09H bDescriptorType 02H wTotalLength 0020H bNumInterfaces 01H bConfigurationValue 01H iConfiguration 00H bmAttributes 80H MaxPower 31H InterfaceDescriptor Field Name bLength 09H bDescriptorType 04H bInterfaceNumber 00H bAlternateSetting 00H bNumEndpoints 02H bInterfaceClass FFH bInterfaceSubClass 00H bInterfaceProtocol 50H iIinterface 00H ...

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Table 3.4.19 Information Returned for the Microcontroller Information Command Microcontroller Information TMP92CZ26 54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H Note: TMP92CF26AXBG share ROM code with TMP92CZ26AXBG. Please be careful Table 3.4.20 Information Returned ...

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Description of the USB boot program operation The boot program loads a user program in Intel Hex format sent from the PC into the internal RAM. When the user program has been loaded successfully, the user program starts executing ...

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Notes on the user program format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, ...

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Others a) USB connector The USB connector must not be connected or disconnected while the boot program is running. b) Software on the PC To download a user program via USB, a USB device driver and special application software ...

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Interrupts Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits the Status Register) and by the built-in interrupt controller. TMP92CF26A has a total of 56 interrupts divided into the following five ...

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Interrupt processing Interrupt specified by DMA start vector ? Interrupt vector calue “V” read interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> ← Level of INTNEST ← INTNEST + 1 PC ← (FFFF00H + V) Interrupt ...

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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), ...

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Table 3.5.1 TMP92CF26A Interrupt Vectors and Micro DMA/HDMA Start Vectors Default Interrupt Source and Source of Type Priority 1 Reset or [SWI0] instruction 2 [SWI1] instruction 3 Illegal instruction or [SWI2] instruction 4 [SWI3] instruction Non 5 [SWI4] instruction maskable ...

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Default Interrupt Source and Source of Type Priority 51 INTADHP: AD most priority conversion end 52 INTAD: AD conversion end 53 INTTC0/INTDMA0: Micro DMA0 /HDMA0 end 54 INTTC1/INTDMA1: Micro DMA1 /HDMA1 end 55 INTTC2/INTDMA2: Micro DMA2 /HDMA2 end 56 INTTC3/INTDMA3: ...

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Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CF26A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.23 DMA controller. Micro DMA processing ...

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Note1: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA ...

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Soft start function The TMP92CF26A can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the ...

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Detailed description of the transfer mode register Mode DMAMn[4: Destination INC mode (DMADn +) ← (DMASn) ← DMACn - 1 DMACn If DMACn = 0 then INTTCn ...

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Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...

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Figure 3.5.3 Block Diagram of Interrupt Controller 92CF26A-76 TMP92CF26A 2009-06-25 ...

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Interrupt priority setting registers Symbol Name Address INT0 INTE0 F0H enable INT1 & INT2 INTE12 D0H enable INT3 & INT4 INTE34 D1H enable INT5 & INT6 INTE56 D2H enable INT7 INTE7 D3H enable INTTA0 & INTTA1 INTETA01 D4H enable ...

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Symbol Name Address INTTB00 & INTETB0 INTTB01 D8H enable INTTB10 & INTETB1 INTTB11 D9H enable INTRX0 & INTES0 INTTX0 DBH enable INTSBI & INTESBIADM INTADM E0H enable INTSPI INTESPI E1H enable INTUSB INTEUSB E3H enable INTALM INTEALM E5H enable INTRTC ...

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Symbol Name Address INTLCD INTELCD EAH enable INTI2S0 & INTEI2S01 INTI2S1 EBH enable INTRSC & INTENDFC INTRDY ECH enable INTP0 INTEP0 EEH enable INTAD & 0INTEAD INTADHP EFH enable Interrupt request flag − − − − ...

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Symbol Name Address INTTC0/INTDMA0 & INTETC01 INTTC1/INTDMA1 F1H /INTEDMA01 enable INTTC2/INTDMA2 & INTETC23 INTTC3/INTDMA3 F2H /INTEDMA23 enable INTTC4/INTDMA4 & INTETC45 INTTC5/INTDMA5 F3H /INTEDMA45 enable INTTC6 & INTTC7 INTETC67 F4H enable INTWD INTWDT F7H enable Interrupt request flag ...

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External interrupt control Symbol Name Address I5EDGE Interrupt F6H INT5EDGE IIMC0 input mode (Prohibit 0: Rising control 0 RMW) 1: Falling Interrupt FAH IIMC1 input mode (Prohibit control 0 RMW) Note 1: Disable INT0 request before changing INT0 pin ...

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SIO receive interrupt control Symbol Name Address SIO F5H Always interrupt SIMC (Prohibit write “0” mode RMW) (Note) control Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX0 edge enable 0 Edge detect INTRX0 1 ...

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Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start vector, as given in Table 3.5.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the ...

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Symbol Name Address DMA0 DMA0V start 100H vector DMA1 DMA1V start 101H vector DMA2 DMA2V start 102H vector DMA3 DMA3V start 103H vector DMA4 DMA4V start 104H vector DMA5 DMA5V start 105H vector DMA6 DMA6V start 106H vector DMA7 DMA7V ...

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Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches “0”. Setting any of the bits in the register DMAB ...

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Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute ...

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DMAC (DMA Controller) The TMP92CF26A incorporates a DMA controller (DMAC) having six channels. This DMAC can realize data transfer faster than the micro DMA function by the 900/H1 CPU. The DMAC has the following features: 1) Six independent channels ...

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Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. SDRAM Controller INTC (Interrupt Controller) Interrupt REQ 7 0 DMAnV →DMAC or micro DMA request source setting DMAR →DMAC or micro DMA soft start setting DMAB →Micro ...

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SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. ...

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HDMADn (DMA Transfer Destination Address Setting Register) The HDMADn register is used to set the DMA transfer destination address. When the destination address is updated by DMA execution, HDMADn is also updated. HDMAD0 to HDMAD5 have the same configuration. ...

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HDMACAn (DMA Transfer Count A Setting Register) The HDMACAn register is used to set the number of times a DMA transfer performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536 ...

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HDMACBn (DMA Transfer Count B Setting Register) The HDMACBn register is used to set the number of times a DMA request made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one ...

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HDMAMn (DMA Transfer Mode Setting Register) The HDMAMn register is used to set the DMA transfer mode. HDMAM0 to HDMAM5 have the same configuration. 7 HDMAMn bit Symbol Read/Write Reset State Function Transfer mode [7:0] HDMAM0 Channel 0 (090CH) ...

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HDMAE (DMA Operation Enable Register) The HDMAE register is used to enable or disable the DMAC operation. Bits correspond to channels Unused channels should be set to “0”. 7 HDMAE bit Symbol (097EH) ...

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DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is requested. Interrupt (DMA) request No Interrupt specified by DMA start vector? Yes Interrupt request F/F clear & bus REQ assert ...

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Bus arbitration The TMP92CF26A includes three controllers (DMA controller, LCD controller, SDRAM controller) that function as bus masters apart from the CPU. These controllers operate independently and assert a bus request as required. The controller that receives a bus ...

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Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to ...

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Note In case of using S/W start with HDMA, transmission start is to set to “1” DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to “0” when HDMA release bus ...

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Considerations for Using More Than One Bus Master In the TMP92CF26A, the LCD controller, SDRAM controller, and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these ...

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Sample 1: Calculation example for CPU + HDMA Conditions: CPU operation speed (f SYS I2S sampling frequency : 48 KHz (60 MHz/25/ KHz) I2S data transfer bit length DMAC channel 0 used to transfer 5 Kbytes from internal ...

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CPU + LDMA The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the CPU and getting a bus acknowledgement. If LDMA is not performed properly, the LCD display function cannot work properly. Therefore, LDMA must ...

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Sample2: Calculation examples for CPU + LDMA Conditions 1: CPU operation speed (f ) SYS Display RAM : Internal RAM Display size : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 ...

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CPU + LDMA + ARDMA The SDRAM controller owns the bus not only when SDRAM is used as the LCD display RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller occupies the ...

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Sample3: Calculation example for CPU + LDMA + ARDMA Conditions: CPU operating speed (f ) SYS Display RAM Display size Display quality Refresh rate SDRAM auto refresh Calculation example: t (LDMA) =((SegNum × × t STOP LHSYNC ...

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CPU + LDMA+ ARDMA + HDMA This is a case in which all the bus masters are active at the same time. Since the LCD display function cannot work properly if the LCD controller cannot perform LDMA properly, the ...

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Sample 4: Calculation example for CPU + LDMA+ ARDMA + HDMA Conditions: CPU operation speed (f SYS Display RAM : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy ...

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HDMATR bit Symbol DMATE (097FH) Read/Write Reset State 0 Timer operation Function 0: Disable 1: Enable Note: Read-modify-write instructions can be used on this register. By writing “87H” to the HDMATR register, the maximum HDMA time is set to ...

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Function of ports The TMP92CF26A I/O port pins are shown in Table 3.7.1. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.7.2 lists the I/O registers ...

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Table 3.7.1 Port Functions (2/3) Number Port Name Pin Name of Pins Port J PJ0 1 PJ1 1 PJ2 1 PJ3 1 PJ4 1 PJ5 1 PJ6 1 PJ7 1 Port K PK0 1 PK1 1 PK2 1 PK3 1 ...

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Table 3.7.1 Port Functions (3/3) Number Port Name Pin Name of Pins Port Z PZ0 1 PZ1 1 PZ2 1 PZ3 1 PZ4 1 PZ5 1 PZ6 1 PZ7 1 I/O R I/O Setting − I/O bit EI_PODDATA − I/O ...

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Table 3.7.2 I/O Port and Specifications (1/4) Port Pin name Port 1 P10 toP17 Input port Output port D8 to D15 bus Port 4 P40 to P47 Output port Output Port 5 P50 to P57 Output port ...

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Table3.7.2 I I/O Port and Specifications (2/4) Port Pin name Port 9 P90, P92 Input port P91 Input port, RXD0 Input P96 Input port P97 Input port P90 to P92 Output port P90 TXD0 Output TXD0 Output (Open-drain) P92 SCLK0 ...

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Table3.7.2 I/O Port and Specifications (3/4) Port Pin name Port G PG0 to PG5 Input port AN0 to AN5 Input ADTRG Input PG3 PG2 MX Output PG3 MY Output Port J PJ5 to PJ6 Input port PJ5 to PJ6 Output ...

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Table 3.7.2 I/O Port and Specifications (4/4) Port Pin name Port R PR0 to PR3 Input port PR0 to PR3 Output port PR0 SPDI Input PR1 SPDO Output PR2 SPCS Output PR3 SPCLK Output Port T PT0 to PT7 Input ...

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Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, ...

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P1 bit Symbol P17 (0004H) Read/Write System Reset State Hot Reset State 7 P1CR bit Symbol P17C P16C (0006H) Read/Write System 0 Reset State Hot Reset − State Function 7 P1FC bit Symbol (0007H) Read/Write System Reset State (Note2) ...

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Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit can be set individually for ...

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P4 bit Symbol P47 (0010H) Read/Write System 0 Reset State Hot Reset − State 7 P4FC bit Symbol P47F (0013H) Read/Write System Reset State 0/1 (Note2) Hot Reset − State Function 7 P4DR bit Symbol P47D (0084H) Read/Write System ...

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Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for ...

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P5 bit Symbol P57 (0014H) Read/Write System 0 Reset State Hot Reset − State 7 P5FC bit Symbol P57F (0017H) Read/Write System Reset State 0/1 (Note2) Hot Reset − State Function 7 P5DR bit Symbol P57D (0085H) Read/Write System ...

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Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose ...

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P6 bit Symbol P67 (0018H) Read/Write System Reset State Hot Reset State 7 P6CR bit Symbol P67C (001AH) Read/Write System 0 Reset State Hot Reset − State Function 7 P6FC bit Symbol P67F (001BH) Read/Write System Reset State 0/1 ...

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Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to ...

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P7CR register P7FC register P7 register EA24, EA25 Read data P7CR register P7FC register P7 register R/W Port read data NDR/ B P7CR register P7FC register P7 register Port read data WAIT Selector Selector ...

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P7 bit Symbol (001CH) Read/Write Data from external port System (Output latch register is Reset State Hot Reset State 7 P7CR bit Symbol (001EH) Read/Write System Reset State Hot Reset State Function 7 P7FC bit Symbol (001FH) Read/Write System ...

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Port 8 (P80 to P87) Ports are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the output latches of P80 to P81, P83 to P87 to “1”. But ...

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P8 bit Symbol P87 (0020H) Read/Write System 1 Reset State Hot Reset − State 7 P8FC bit Symbol P87F (0023H) Read/Write System 0 Reset State Hot Reset − State 0: Port 0: Port Function 1: <P87F2> 1: <P86F2> 7 ...

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Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on a bit basis using the control register. Each bit can be set individually for input or output. Resetting sets ...

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Reset Direction control (on bit basis) P9CRwrite Function control (on bit basis) P9FCwrite S A Output latch Selector P9 write B SCLK0 output Selector P9 read SCLK0 input Reset Function control TSICR0<PXEN> P9FC write TSICR0<TSI7> P9 read Rising/Falling INT4 edge-ditection ...

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P9 bit Symbol P97 (0024H) Read/Write R System Data from external Reset State port Hot Reset − State 7 P9CR bit Symbol (0026H) Read/Write System Reset State Hot Reset State Function 7 P9FC bit Symbol (0027H) Read/Write System Reset ...

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Port A (PA0 to PA7) Ports are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports can also Keyboard interface,operate a Key-on wake-up function. ...

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PA bit Symbol PA7 (0028H) Read/Write System Reset State Hot Reset State 7 PAFC bit Symbol PA7F (002BH) Read/Write System 0 Reset State Hot Reset − State Function 7 PADR bit Symbol PA7D (008AH) Read/Write System 1 Reset State ...

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Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port input port. It also sets all bits of the output ...

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PC1 (INT1, TA0IN), PC3 (INT3, TA2IN) Reset Direction control PCCR write Function control PCFCwrite S Output latch PCwrite Selector PC read Level/edge selection INT1 INT3 Rising/Falling selection IIMC<I1LE, I1EDGE> TA0IN TA2IN Figure 3.7.21 Port C1,C3 92CF26A-134 ...

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PC4 (EA26), PC5 (EA27), PC6 (EA28) Reset Direction control (on bit basis) PCCRwrite Function control (on bit basis) PCFC write Output latch Selector B PC write C EA26 EA27 EA28 PC read Figure 3.7.22 Port C4, ...

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Symbol PC PC7 Read/Write (0030H) System Reset State Hot Reset State 7 bit Symbol PCCR PC7C Read/Write (0032H) System 0 Reset State Hot Reset − State Function 7 bit Symbol PCFC PC7F Read/Write (0033H) System 0 Reset State ...

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Port F (PF0 to PF5, PF7) Ports are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF5 to be input ports. It also sets all bits ...

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Reset Direction control (on bit basis) PFCR write Function control (on bit basis) PFFC write Output latch Selector PF write B I2S0CKO output S I2S1CKO output Selector PF read Figure 3.7.25 Port F0, F3 Reset Direction control ...

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Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Reset Function control (on bit basis) PFFC write S Output latch SDCLK PF write ...

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Symbol PF PF7 Read/Write (003CH) R/W System 1 Reset State Hot Reset − State 7 bit Symbol PFCR Read/Write (003EH) System Reset State Hot Reset State Function 7 PFFC bit Symbol PF7F (003FH) Read/Write W System 1 Reset ...

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Port G (PG0 to PG5) PG0 to PG5 are 6-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD ...

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PG Bit Symbol (0040H) Read/Write System Reset State Hot Reset State Note: The input channel selection of the AD converter and the permission of for ADTRG input are set by AD converter mode register ADMOD1. 7 PGFC Bit Symbol ...

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Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as a ...

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Reset Direction control PJCR write Function control PJFC write Output latch Selector PJ write B NDALE, NDCLE output S Selector P J read Figure 3.7.32 Port J5,J6 92CF26A-144 B A TMP92CF26A PJ5 (NDALE), PJ6 (NDCLE) 2009-06-25 ...

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PJ bit Symbol PJ7 (004CH) Read/Write System Data from external port Reset State 1 (Output latch register is Hot Reset − State 7 PJCR bit Symbol (004EH) Read/Write System Reset State Hot Reset State Function 7 bit Symbol PJFC ...

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Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK7 pins output “0”. In addition to functioning as an output port function, port K also ...

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PK bit Symbol PK7 (0050H) Read/Write System 0 Reset State Hot Reset − State 7 PKFC bit Symbol PK7F (0053H) Read/Write System 0 Reset State Hot Reset − State Function 0:Port 0:Port 1:LGOE2 1:LGOE1 7 PKDR bit Symbol PK7D ...

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Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addition to functioning as a general-purpose output port, port L can ...

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PL bit Symbol PL7 (0054H) Read/Write System 0 Reset State Hot Reset − State 7 PLFC bit Symbol PL7F PL6F (0057H) Read/Write System 0 Reset State Hot Reset − State Function 7 PLDR bit Symbol PL7D PL6D (0095H) Read/Write ...

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Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and PM1, PM2 and PM7 pins output “1”. In addition to functioning as an output ports, port M ...

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Reset Function control (on bit basis) PMFC write S Output latch A Selector B PM write PM read A S MLDALM Selector B ALARM Figure 3.7.39 Port M2 Reset Function control (on bit basis) PMFC write S Output latch PM ...

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PM bit Symbol PM7 (0058H) Read/Write R/W System 1 Reset State Hot Reset − State 7 bit Symbol PMFC PM7F Read/Write (005BH) W System 0 Reset State Hot Reset − State Function 0: Port 1: PWE 7 PMDR bit ...

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Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port input port. In addition to functioning as a general-purpose I/O ...

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PN bit Symbol PN7 (005CH) Read/Write System Reset State Hot Reset State 7 PNCR bit Symbol PN7C (005EH) Read/Write System 0 Reset State Hot Reset − State Function 7 PNFC bit Symbol PN7F (005FH) Read/Write System 0 Reset State ...

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Port P (PP1 to PP7) Ports are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port input port and output latch to “0”. In ...

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Reset Direction control (on bit basis) PPCR write Function control (on bit basis) PPFC write Output latch Selector B PP write TA7OUT S Selector PP read A Level/edge selection INT5 Rising/Falling selection IIMC<I5LE, I5EDGE> Figure 3.7.45 Port ...

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Reset Function control (on bit basis) PPFC write Output latch Selector PP write B TB0OUT0 output TB1OUT0 output Figure 3.7.47 Port P6, P7 92CF26A-157 TMP92CF26A PP6 (TB0OUT0) PP7 (TB1OUT0) 2009-06-25 ...

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PP bit Symbol PP7 (0060H) Read/Write System 0 Reset State Hot Reset − State 7 PPCR bit Symbol (0062H) Read/Write System Reset State Hot Reset State Function 7 PPFC bit Symbol PP7F (0063H) Read/Write System 0 Reset State Hot ...

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Port R (R0 to R3) Ports are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port input port and output latch to “0”. In ...

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Reset Direction control (on bit basis) PRCR write Function control (on bit basis) PRFC write Output latch Selector B PR write SPDO, S SPCS , SPCLK Selector PR read Figure 3.7.50 Port 92CF26A-160 SPICT<CEN> ...

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PR bit Symbol (0064H) Read/Write System Reset State Hot Reset State 7 PRCR bit Symbol (0066H) Read/Write System Reset State Hot Reset State Function 7 PRFC bit Symbol (0067H) Read/Write System Reset State Hot Reset State Function 7 PRDR ...

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Port T (PT0 to PT7) Ports are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports input port and output latch to “0”. In ...

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PT bit Symbol PT7 (00A0H) Read/Write System Reset State Hot Reset State 7 PTCR bit Symbol PT7C PT6C (00A2H) Read/Write System 0 Reset State Hot Reset − State Function 7 bit Symbol PTFC PT7F Read/Write (00A3H) System 0 Reset ...

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Port U (PU0 to PU7) Ports are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port input port and output latch to “0”. In ...

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Reset Direction control (on bit basis) PUCR wirte Function control (on bit basis) PUFC write Output latch Selector B PU write LD21 S B Selector PU read A Figure 3.7.55 Port U5 92CF26A-165 TMP92CF26A PU5 (LD21) 2009-06-25 ...

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PU Bit Symbol PU7 (00A4H) Read/Write System Reset State Hot Reset State 7 PUCR Bit Symbol PU7C (00A6H) Read/Write System 0 Reset State Hot Reset − State Function 7 PUFC Bit Symbol PU7F (00A7H) Read/Write System 0 Reset State ...

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Port V (PV0 to PV4, PV6, PV7) Ports V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V0 to V2, V6 and V7 to ...

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Reset R Output latch PV write PV read Figure 3.7.58 Port V3, V4 Reset Direction control (on bit basis) PVCR write Function control (on bit basis) PVFC write Output latch Selector PV write B SDA,SCL output S ...

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PV bit Symbol PV7 (00A8H) Read/Write R/W Data from external port System (Output latch register is Reset State cleared to “0”) Hot Reset − State 7 PVCR bit Symbol PV7C (00AAH) Read/Write System 0 Reset State Hot Reset − ...

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Port W (PW0 to PW7) Ports are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports input port and output latch to “0”. Setting ...

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PW bit Symbol PW7 Read/Write (00ACH) System Reset State Hot Reset State 7 PWCR bit Symbol PW7C (00AEH) Read/Write System 0 Reset State Hot Reset − State Function 7 PWFC bit Symbol PW7F (00AFH) Read/Write System 0 Reset State ...

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Port X (PX4, PX5 and PX7) Ports X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports X5 and X7 to input port and output latch to “0”. ...

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Reset Direction control (on bit basis) PXCR write Function control (on bit basis) PXFC write R Output latch PX write Selector PX read X1USB input Figure 3.7.64 Port X5, X7 92CF26A-173 PX5 (X1USB) PX7 TMP92CF26A 2009-06-25 ...

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PX bit Symbol PX7 (00B0H) Read/Write R/W System Data from external port Reset State (Output latch register is cleared to “0”) Hot Reset State 7 PXCR bit Symbol PX7C (00B2H) Read/Write W System 0 Reset State Hot Reset − ...

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Port Z (PZ0 to PZ7) Ports are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports input port and output latch to “0”. In ...

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Reset Debug mode Direction control (on bit basis) PZCR write Output latch Selector PZ write B EO_MCUDATA EO_MCUREQ S Selector PZ read Figure 3.7.67 Port 92CF26A-176 PZ6(EO_MCUDATA) PZ7(EO_MCUREQ TMP92CF26A 2009-06-25 ...

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PZ bit Symbol PZ7 (0068H) Read/Write System Reset State Hot Reset State 7 PZCR bit Symbol PZ7C PZ6C (006AH) Read/Write System 0 Reset State Hot Reset − State Function 7 PZDR bit Symbol PZ7D PZ6D (009AH) Read/Write System 1 ...

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Memory Controller (MEMC) 3.8.1 Functional Overview The TMP92CF26A has a memory controller with the following features to control four programmable address spaces: (1) Four programmable address spaces The MEMC can specify a start address and a block size for ...

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Control Rregisters and Memory Access Operations After Reset This section describes the registers to control the memory controller, their reset states and the necessary settings after reset. (1) Control Registers The control registers of the memory controller are listed ...

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B0CSL Bit Symbol B0WW3 B0WW2 (0140H) Read/Write Reset State 0 B0CSH Bit Symbol B0E (0141H) Read/Write R/W Reset State 0 MAMR0 Bit Symbol M0V20 (0142H) Read/Write Reset State 1 MSAR0 Bit Symbol M0S23 (0143H) Read/Write Reset State 1 B1CSL ...

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BEXCSL Bit Symbol BEXWW3 (0158H) Read/Write Reset State 0 BEXCSH Bit Symbol (0159H) Read/Write Reset State PMEMCR Bit Symbol (0166H) Read/Write Reset State CSTMGCR Bit Symbol (0168H) Read/Write Reset State WRTMGCR Bit Symbol (0169H) Read/Write Reset State RDTMGCR0 Bit ...

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Memory Access Operations After Reset After reset, external memory is accessed using the initial data bus width that is determined by the AM1 and AM0 pins. The settings of the AM1 and AM0 pins and their corresponding operation modes ...

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Basic Functions and Register Settings This section describes some of the memory controller functions, such as setting the address range for each address space, associating memory to the selected space and setting the number of wait states to be ...

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Memory Address Mask Registers Figure 3.8.3 shows the Memory Address Mask registers. MAMR0 to MAMR3 are used to determine the sizes of the CS0 to CS3 spaces by setting particular bits in MAMR0 to MAMR3 to mask the corresponding ...

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Setting the start addresses and address ranges An example of specifying a 64-Kbyte address space starting from 010000H for the CS0 space: Set 01H in the MSAR0<S23:S16> bits that corresponds to the upper 8 bits of the start address. ...

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Table 3.8.3 Valid Block Sizes for Each CS Space Size (Byte) 256 512 space ○ ○ ○ CS0 ○ ○ CS1 ○ CS2 ○ CS3 Note: The “ Δ ” symbol indicates the sizes that may not ...

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Memory specification Setting the BnCSH<BnOM1:BnOM0> bits specifies the memory type that is associated with each address spaces. The interface signal that corresponds to the specified memory type is generated. The memory type is specified as follows: BnCSH<BnOM1:0> BnOM1 BnOM0 ...

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Operand Start Operand Data Size (bit) Address ...

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Wait control The external bus cycle completes in two states at minimum ( without inserting a wait state. Setting up the BnCSL<BnWW3:BnWW0> bits specifies the number of wait states to be inserted in a write cycle, ...

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Recovery cycle (data hold time) control For some memory, the data hold time after when the read cycle is defined by the AC specification. This may lead to data conflicts. Thus, to avoid this problem, a single dummy cycle ...

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Timing adjustment function for control signals This function allows for the timing adjustment of the rising and falling edges of the , , , CSn CSZx CSXx W RD time requirements of memories. As for the ...

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RDTMGCR0/1<BnTCRS1:BnTCRS0> TCRS:The delay from CSn to RD,SRxxB. T1 SDCLK (80MHz) A23 to A0 CSn TAC SRxxB Read cycle D15 to D0 WRxx Write SRWR cycle SRxxB D15 to D0 Note: Wait states (TWs) ...

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Basic bus timing (a) External bus read/write cycle (0 wait state) T1 SDCLK (60 MHz) CSn A23 SRxxB D15 SRWR SRxxB WRxx D15 to D0 (b) External bus read/write cycle (1 wait ...

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External bus read cycle (1 wait state + TAC: 1×1/f External bus write cycle (1 wait state + TAC: 1×1/f T1 SDCLK (80 MHz) TAC CSn A23 SRxxB D15 to D0 SRWR , SRxxB WRxx D15 ...

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External bus read/write cycle (4 wait states + T1 SDCLK (80 MHz) CSn A23 SRxxB D15 to D0 SRWR , SRxxB WRxx D15 to D0 WAIT (f) External bus read cycle (4 wait states + External ...

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External memory connections Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR flash to the TMP92CF26A. TMP92CF26A RD SRLLB SRLUB SRWR [15:0] Not connect ...

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Controlling the Page Mode Access to ROM This section describes page mode access operations to ROM and the required register settings. The page mode operation to ROM is specified by PMEMCR. (1) Operations and register settings The TMP92CF26A supports ...

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On-Chip Boot ROM Control This section describes the on-chip boot ROM. For the program specification of boot ROM, refer to Section 3.4, Boot ROM. (1) BOOT mode The TMP92CF26A boots in BOOT mode following the AM1 and AM0 settings ...