TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 431

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(c) Control transfer type
(c-1) Setup stage
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transactions. The UDC executes each transaction while managing three stages in
hardware. Control transfer has the 3 types given below depending on whether there
is data stage or not, and on direction.
vendor request must have an intervening CPU controlling the UDC.
becomes SETUP.
Control transfer type is configured in the three stages below.
Data stage is sometimes skipped. Each stage is configured in one or several
The 3 transfer sequences are shown in Figure 3.16.6, Figure 3.16.7 and
Figure 3.16.8.
The UDC automatically answers standard requests in hardware. Class request and
Below is the control flow in the UDC and the control flow in the intervening CPU.
Setup stage is the same as transmission bulk transaction except that token ID
However, control flow in the UDC is different.
Control flow
Below is the control flow in the UDC when SETUP token is received.
1. SETUP token packet is received and address, endpoint number and error are
2. STATUS register state is confirmed.
Setup stage
Data stage
Status stage
Control read transfer type
Control write transfer type
Control write transfer type (No data stage)
Token: SETUP
Data: DATA 0
Handshake: ACK
State return to IDLE only if it is INVALID state.
In bulk transfer mode, receiving data is enabled by STATUS registers value and
FIFO condition. However, in SETUP stage, STATUS is returned to READY and
accessing from the CPU to FIFO is always prohibited and internal FIFO of
endpoint 0 is cleared. It also prepares for following dataphase.
If the CPU accesses Setup Received registers in the UDC, it recognizes as Device
request as received, and accessing from the CPU to EP0 is enabled.
This function is for receiving a new request when the current device request has
not finished normally.
confirmed. It also checks whether the relevant endpoint is in control transfer
mode.
92CF26A-429
TMP92CF26A
2009-06-25