TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 310

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TB1FFCR
(1193H)
A read-
modify-write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
TB1FF0 control
Inverted when UC12 value is captured into TB1CP0H/L
TB1FF0 control
Inverted when UC12 value is captured into TB1CP1H/L
Always write “11”
*Always read as “11”.
TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG1H/L
Timer flip-flop control(TB1FF0)
TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG0H/L
<TB1FF0C1:0>
7
−
1
<TB1C0T1>
<TB1C1T1>
<TB1E0T1>
<TB1E1T1>
W*
TMRB1 Flip-Flop Control Register
6
−
1
Figure 3.13.7 Register for TMRB
TB1FF0 inversion trigger
0: Disable trigger
1: Enable trigger
When
capture
UC12 to
TB1CP1H/L
TB1C1T1
92CF26A-308
00
01
10
11
0
1
5
0
0
1
0
1
0
1
Invert
Set to “11”
Clear to “00”
Don’t care
Disable trigger
Enable trigger
Disable trigger
Enable trigger
Disable trigger
Enable trigger
When
capture
UC12 to
TB1CP0H/L
Disable trigger
Enable trigger
TB1C0T1
4
0
R/W
When UC12
matches
with
TB1RG1H/L
TB1E1T1
3
0
When UC12
matches
with
TB1RG0H/L
TB1E0T1
2
0
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
*Always read as “11”.
TB1FF0C1
1
1
W*
TMP92CF26A
TB1FF0C0
2009-06-25
0
1