TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 675

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SCLK cycle
Output data → SCLK rising/ falling
SCLK rising/ falling → Output data hold
SCLK rising/ falling → Input data hold
SCLK rising/ falling → Input data valid
Input data valid → SCLK rising/ falling
SCLK cycle (Programmable)
Output data → SCLK rising/ falling
SCLK rising/ falling → Output data hold
SCLK rising/ falling → Input data hold
SCLK rising/ falling → Input data valid
Input data valid → SCLK rising/ falling
4.3.5
(Input falling mode)
Input rising mode
Output mode/
Output data
Input data
Parameter
Parameter
Serial channel timing
SCLK
SCLK
RXD
TXD
(1) SCLK input mode (I/O interface mode)
(2) SCLK output mode (I/O interface mode)
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
OSS
OHS
HSR
SRD
RDS
OHS
SCY
SCY
OSS
HSR
SRD
RDS
t
OSS
t
Valid
SCY
t
t
SCY
0
SCY
0
92CF26A-673
t
t
SCY
SCY
t
/2 − 4T − 30
2T + 10
1T + 50
OHS
/2 + 2T -20
Min
Min
16T
16T
20
/2 − 40
/2 − 40
t
0
SRD
Variable
Variable
t
RDS
Valid
t
SCY
1
1
t
SCY
8192T
Max
Max
− 1T − 50
− 20
t
HSR
80 MHz 60 MHz Unit
80 MHz 60 MHz Unit
Valid
137.5
62.5
200
105
180
200
20
35
20
60
60
2
0
2
36.4
266
146
246
266
199
43
20
93
93
66
0
TMP92CF26A
Valid
3
ns
ns
3
2009-06-25